Common-case optimized memory hierarchy for data centers and HPC systems

The memory hierarchy is predicted to consume up to 40% to 70% of total system power in future data centers and high performance computing (HPC) systems; as such, it is time to rethink memory system designs. Conventional memory system designs in existing systems often seek to provide uniform performance across time and space. While this design approach is simple, which benefits hardware implementation, the overheads of uncommon operations often dictate overall memory energy and performance. This dissertation explores across the memory hierarchy common-case optimized memory design, which reduces overall overheads by reducing common overheads at the cost of increasing uncommon overheads. For latency-optimized on-chip caches, which require long-latency correction to ensure reliable accesses during low voltage execution, this dissertation reduces common-case correction latency by proposing architectural techniques such as correction prediction, at the cost of increasing uncommon-case correction latency due to occasional operations such as misprediction recovery. For bandwidth-optimized 3D DRAMs, which are power-hungry due to high access frequency, this dissertation de- scribes new data layout and power management policies to improve overall memory access energy-efficiency at the cost of increasing uncommon-case access latencies. For capacity-optimized server main memory, which contains 100’s to 1000’s of memory chips to provide high capacity and, therefore, needs expensive fault-tolerance, this dissertation proposes an adaptive architecture that minimizes energy when memory contains no or minor fault, at the cost of increasing energy as faults slowly accumulate. Finally, for emerging density-optimized NVRAMs, which suffer from very high random bit error rates, this dissertation describes a server memory architecture that reuses the redundant memory budgeted for memory chip failure protection to accelerate the expensive bit error correction before memory chip(s) fail at the cost of increasing correction overheads after memory chip(s) fail.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2018

Author dc:creator

• Jian, Xun

Contributors dc:contributor

• Kumar, Rakesh
• Torrellas, Josep
• Hanumolu, Pavan K.
• Sridharan, Vilas

• Memory hierarchy
• Computer architecture
• Energy-efficient computing
• Fault-tolerant computing

Statement dc:rights

• Copyright 2017 Xun Jian

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/99448

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/99448