Design and implementation of a phase locked loop for high-speed serial links

Recent advances in the semiconductor industry and process technology scaling have increased the demand for fast, robust computing. The thirst for high-processing, low power ICs is ever increasing. This has pushed the demand for high data rates in wireless and wireline communication systems in the multi-Gbps range. With higher data rates, the I/O links need to scale proportionally. However, the I/O channel bandwidth has not scaled appropriately making it the biggest bottleneck in high-speed links. Parallel links have not been able to match this increasing system performance due to issues such as crosstalk, timing skew and packaging costs. Thus there is a need for high-speed serial links. For high-speed transmission of data, there arises a need for high-speed on chip clocking circuits making the use of Phase-Locked Loops (PLLs) imperative. This thesis includes an overview of high-speed links along with the need for PLLs. An in-depth understanding of PLL theory, loop dynamics and behavioral and transistor level simulation follows. Performance metrics such as phase noise, random jitter and deterministic jitter are discussed. Finally, this thesis concludes with an insight into All Digital Phase-Locked Loops (ADPLLs).

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2016

Author dc:creator

• Mehta, Rushabh Ravindra

Contributors dc:contributor

• Schutt-Ainé, José

• Phase-Locked Loops (PLL)
• High-Speed Serial Links
• Serial Links

Statement dc:rights

• Copyright 2016 Rushabh Mehta

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/90822

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F90822