{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/90822"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/90822","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Design and implementation of a phase locked loop for high-speed serial links","abstract":"The student, Rushabh Mehta, accepted the attached license on 2016-04-25 at 13:40.","abstract_html":"The student, Rushabh Mehta, accepted the attached license on 2016-04-25 at 13:40.","abstract_has_math":false,"creators":["Mehta, Rushabh Ravindra"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Schutt-Ainé, José"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2016,"date_issued":"2016-07-07T20:27:59Z","date_published":"2016-07-07T20:27:59Z","updated_at":"2026-07-22T22:26:34Z","subjects":["Phase-Locked Loops (PLL)","High-Speed Serial Links","Serial Links"],"languages":["en"],"rights":["Copyright 2016 Rushabh Mehta"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/90822","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Schutt-Ainé, José"]},{"key":"dc:creator","label":"Author","values":["Mehta, Rushabh Ravindra"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2016-07-07T20:27:59Z","2018-07-08T09:15:20Z","2016-04-27","2016-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Phase-Locked Loops (PLL)","High-Speed Serial Links","Serial Links"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2016 Rushabh Mehta"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/90822"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The student, Rushabh Mehta, accepted the attached license on 2016-04-25 at 13:40.","The student, Rushabh Mehta, submitted this Thesis for approval on 2016-04-25 at 13:46.","This Thesis was approved for publication on 2016-04-27 at 14:52.","DSpace SAF Submission Ingestion Package generated from Vireo submission #9475 on 2016-07-07 at 13:50:45","Made available in DSpace on 2016-07-07T20:27:59Z (GMT). No. of bitstreams: 2 MEHTA-THESIS-2016.pdf: 13984347 bytes, checksum: 4ecb06c5c270bc1beffb061eeae85eef (MD5) LICENSE.txt: 4210 bytes, checksum: e6aea67d4e02d64f06671bb40ada2274 (MD5) Previous issue date: 2016-04-27","Recent advances in the semiconductor industry and process technology scaling have increased the demand for fast, robust computing. The thirst for high-processing, low power ICs is ever increasing. This has pushed the demand for high data rates in wireless and wireline communication systems in the multi-Gbps range. With higher data rates, the I/O links need to scale proportionally. However, the I/O channel bandwidth has not scaled appropriately making it the biggest bottleneck in high-speed links. Parallel links have not been able to match this increasing system performance due to issues such as crosstalk, timing skew and packaging costs. Thus there is a need for high-speed serial links. For high-speed transmission of data, there arises a need for high-speed on chip clocking circuits making the use of Phase-Locked Loops (PLLs) imperative. This thesis includes an overview of high-speed links along with the need for PLLs. An in-depth understanding of PLL theory, loop dynamics and behavioral and transistor level simulation follows. Performance metrics such as phase noise, random jitter and deterministic jitter are discussed. Finally, this thesis concludes with an insight into All Digital Phase-Locked Loops (ADPLLs).","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2018-05-01","Embargo set by: Seth Robbins for item 93174 Lift date: 2018-07-07T20:28:14Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 93174 Lift date: 2018-07-07T20:35:34Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 93174 on 2018-07-08T09:15:20Z."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Design and implementation of a phase locked loop for high-speed serial links"]}]}],"canonical_facts":{"dc:contributor":["Schutt-Ainé, José"],"dc:creator":["Mehta, Rushabh Ravindra"],"dc:date":["2016-07-07T20:27:59Z","2018-07-08T09:15:20Z","2016-04-27","2016-05"],"dc:description":["The student, Rushabh Mehta, accepted the attached license on 2016-04-25 at 13:40.","The student, Rushabh Mehta, submitted this Thesis for approval on 2016-04-25 at 13:46.","This Thesis was approved for publication on 2016-04-27 at 14:52.","DSpace SAF Submission Ingestion Package generated from Vireo submission #9475 on 2016-07-07 at 13:50:45","Made available in DSpace on 2016-07-07T20:27:59Z (GMT). No. of bitstreams: 2 MEHTA-THESIS-2016.pdf: 13984347 bytes, checksum: 4ecb06c5c270bc1beffb061eeae85eef (MD5) LICENSE.txt: 4210 bytes, checksum: e6aea67d4e02d64f06671bb40ada2274 (MD5) Previous issue date: 2016-04-27","Recent advances in the semiconductor industry and process technology scaling have increased the demand for fast, robust computing. The thirst for high-processing, low power ICs is ever increasing. This has pushed the demand for high data rates in wireless and wireline communication systems in the multi-Gbps range. With higher data rates, the I/O links need to scale proportionally. However, the I/O channel bandwidth has not scaled appropriately making it the biggest bottleneck in high-speed links. Parallel links have not been able to match this increasing system performance due to issues such as crosstalk, timing skew and packaging costs. Thus there is a need for high-speed serial links. For high-speed transmission of data, there arises a need for high-speed on chip clocking circuits making the use of Phase-Locked Loops (PLLs) imperative. This thesis includes an overview of high-speed links along with the need for PLLs. An in-depth understanding of PLL theory, loop dynamics and behavioral and transistor level simulation follows. Performance metrics such as phase noise, random jitter and deterministic jitter are discussed. Finally, this thesis concludes with an insight into All Digital Phase-Locked Loops (ADPLLs).","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2018-05-01","Embargo set by: Seth Robbins for item 93174 Lift date: 2018-07-07T20:28:14Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","Embargo set by: Seth Robbins for item 93174 Lift date: 2018-07-07T20:35:34Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 93174 on 2018-07-08T09:15:20Z."],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/90822"],"dc:language":["en"],"dc:rights":["Copyright 2016 Rushabh Mehta"],"dc:subject":["Phase-Locked Loops (PLL)","High-Speed Serial Links","Serial Links"],"dc:title":["Design and implementation of a phase locked loop for high-speed serial links"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:34Z"}