System-level design, simulation and measurement for high-speed data links

The era of the internet-of-things (IOT) is expanding the utilization of mobile and cloud computing to a global scale. The enormous data transport places a huge design overhead in building low-cost, low-power, low-error-rate high-speed data links. This thesis provides a system-level overview of the design, simulation, and measurement of high-speed digital applications in the context of signal integrity. Examples are provided to demonstrate the design approach and trade-offs made to arrive at the results. Modeling and simulation methodologies for high-speed interconnect are discussed and studied, using both conformal mapping and the variational method in closed-form solutions, with examples provided to study the frequency-dependent channel effects in high-speed digital systems. Detailed processes along with examples are presented at the end to illustrate some real-world issues many engineers will face when characterizing and measuring high-speed data links.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2016

Author dc:creator

• Yang, Jerry

Contributors dc:contributor

• Schutt-Ainé, José E.

• High-Speed
• Data Links
• SerDes
• System Design
• Interconnect Modeling
• Simulation
• Measurement
• Eye Diagram
• Jitter and Noise
• Signal Integrity
• Embedding
• De-embedding
• Real-Time Scope

Statement dc:rights

• Copyright 2015 Jerry Yang

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/89204

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/89204