{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/89204"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/89204","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"System-level design, simulation and measurement for high-speed data links","abstract":"The era of the internet-of-things (IOT) is expanding the utilization of mobile and cloud computing to a global scale. The enormous data transport places a huge design overhead in building low-cost, low-power, low-error-rate high-speed data links. This thesis provides a system-level overview of the design, simulation, and measurement of high-speed digital applications in the context of signal integrity. Examples are provided to demonstrate the design approach and trade-offs made to arrive at the results. Modeling and simulation methodologies for high-speed interconnect are discussed and studied, using both conformal mapping and the variational method in closed-form solutions, with examples provided to study the frequency-dependent channel effects in high-speed digital systems. Detailed processes along with examples are presented at the end to illustrate some real-world issues many engineers will face when characterizing and measuring high-speed data links.","abstract_html":"The era of the internet-of-things (IOT) is expanding the utilization of mobile and cloud computing to a global scale. The enormous data transport places a huge design overhead in building low-cost, low-power, low-error-rate high-speed data links. This thesis provides a system-level overview of the design, simulation, and measurement of high-speed digital applications in the context of signal integrity. Examples are provided to demonstrate the design approach and trade-offs made to arrive at the results. Modeling and simulation methodologies for high-speed interconnect are discussed and studied, using both conformal mapping and the variational method in closed-form solutions, with examples provided to study the frequency-dependent channel effects in high-speed digital systems. Detailed processes along with examples are presented at the end to illustrate some real-world issues many engineers will face when characterizing and measuring high-speed data links.","abstract_has_math":false,"creators":["Yang, Jerry"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engineering","degree_department":null,"school":null,"contributors":["Schutt-Ainé, José E."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2016,"date_issued":"2016-03-02T21:06:33Z","date_published":"2016-03-02T21:06:33Z","updated_at":"2026-07-22T22:26:32Z","subjects":["High-Speed","Data Links","SerDes","System Design","Interconnect Modeling","Simulation","Measurement","Eye Diagram","Jitter and Noise","Signal Integrity","Embedding","De-embedding","Real-Time Scope"],"languages":["en"],"rights":["Copyright 2015 Jerry Yang"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/89204","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Schutt-Ainé, José E."]},{"key":"dc:creator","label":"Author","values":["Yang, Jerry"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2016-03-02T21:06:33Z","2018-03-03T10:15:31Z","2015-11-23","2015-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["High-Speed","Data Links","SerDes","System Design","Interconnect Modeling","Simulation","Measurement","Eye Diagram","Jitter and Noise","Signal Integrity","Embedding","De-embedding","Real-Time Scope"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2015 Jerry Yang"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/89204"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The era of the internet-of-things (IOT) is expanding the utilization of mobile and cloud computing to a global scale. The enormous data transport places a huge design overhead in building low-cost, low-power, low-error-rate high-speed data links. This thesis provides a system-level overview of the design, simulation, and measurement of high-speed digital applications in the context of signal integrity. Examples are provided to demonstrate the design approach and trade-offs made to arrive at the results. Modeling and simulation methodologies for high-speed interconnect are discussed and studied, using both conformal mapping and the variational method in closed-form solutions, with examples provided to study the frequency-dependent channel effects in high-speed digital systems. Detailed processes along with examples are presented at the end to illustrate some real-world issues many engineers will face when characterizing and measuring high-speed data links.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2017-12-01","The student, Jerry Yang, accepted the attached license on 2015-11-18 at 14:01.","The student, Jerry Yang, submitted this Thesis for approval on 2015-11-18 at 15:16.","This Thesis was approved for publication on 2015-11-23 at 15:05.","DSpace SAF Submission Ingestion Package generated from Vireo submission #8803 on 2016-03-02 at 14:13:12","Made available in DSpace on 2016-03-02T21:06:33Z (GMT). No. of bitstreams: 2 YANG-THESIS-2015.pdf: 16037285 bytes, checksum: 38895b7ae0c186b21ecb9aa4f2f2e979 (MD5) LICENSE.txt: 4207 bytes, checksum: a052190ef8bc330ac85778c71cd68a82 (MD5) Previous issue date: 2015-11-23","Embargo set by: Seth Robbins for item 91407 Lift date: 2018-03-02T21:07:27Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Limited Restriction Lifted for Item 91407 on 2018-03-03T10:15:31Z."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["System-level design, simulation and measurement for high-speed data links"]}]}],"canonical_facts":{"dc:contributor":["Schutt-Ainé, José E."],"dc:creator":["Yang, Jerry"],"dc:date":["2016-03-02T21:06:33Z","2018-03-03T10:15:31Z","2015-11-23","2015-12"],"dc:description":["The era of the internet-of-things (IOT) is expanding the utilization of mobile and cloud computing to a global scale. The enormous data transport places a huge design overhead in building low-cost, low-power, low-error-rate high-speed data links. This thesis provides a system-level overview of the design, simulation, and measurement of high-speed digital applications in the context of signal integrity. Examples are provided to demonstrate the design approach and trade-offs made to arrive at the results. Modeling and simulation methodologies for high-speed interconnect are discussed and studied, using both conformal mapping and the variational method in closed-form solutions, with examples provided to study the frequency-dependent channel effects in high-speed digital systems. Detailed processes along with examples are presented at the end to illustrate some real-world issues many engineers will face when characterizing and measuring high-speed data links.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2017-12-01","The student, Jerry Yang, accepted the attached license on 2015-11-18 at 14:01.","The student, Jerry Yang, submitted this Thesis for approval on 2015-11-18 at 15:16.","This Thesis was approved for publication on 2015-11-23 at 15:05.","DSpace SAF Submission Ingestion Package generated from Vireo submission #8803 on 2016-03-02 at 14:13:12","Made available in DSpace on 2016-03-02T21:06:33Z (GMT). No. of bitstreams: 2 YANG-THESIS-2015.pdf: 16037285 bytes, checksum: 38895b7ae0c186b21ecb9aa4f2f2e979 (MD5) LICENSE.txt: 4207 bytes, checksum: a052190ef8bc330ac85778c71cd68a82 (MD5) Previous issue date: 2015-11-23","Embargo set by: Seth Robbins for item 91407 Lift date: 2018-03-02T21:07:27Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Limited Restriction Lifted for Item 91407 on 2018-03-03T10:15:31Z."],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/89204"],"dc:language":["en"],"dc:rights":["Copyright 2015 Jerry Yang"],"dc:subject":["High-Speed","Data Links","SerDes","System Design","Interconnect Modeling","Simulation","Measurement","Eye Diagram","Jitter and Noise","Signal Integrity","Embedding","De-embedding","Real-Time Scope"],"dc:title":["System-level design, simulation and measurement for high-speed data links"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engineering"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:32Z"}