Layout Extraction Including Substrate Parasitics for ESD Protection Circuits and Design Rule Checking

ESD design rule checking is different from the conventional design rule checking in that not only different rules have to be applied for different components in the ESD protection circuit, but also style of layout is of utmost importance to ensure uniform current distribution during ESD events. ESDRC first employs iLEX to extract the netlist from layout and identify the functionality of each layout object through LVS of the extracted netlist and the schematic. Specific ESD design rules are then checked for each layout object identified.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Li, Qiao

Contributors dc:contributor

• Sun-Mo (Steve) Kang

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9996651

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81993