{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81993"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81993","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Layout Extraction Including Substrate Parasitics for ESD Protection Circuits and Design Rule Checking","abstract":"ESD design rule checking is different from the conventional design rule checking in that not only different rules have to be applied for different components in the ESD protection circuit, but also style of layout is of utmost importance to ensure uniform current distribution during ESD events. ESDRC first employs iLEX to extract the netlist from layout and identify the functionality of each layout object through LVS of the extracted netlist and the schematic. Specific ESD design rules are then checked for each layout object identified.","abstract_html":"ESD design rule checking is different from the conventional design rule checking in that not only different rules have to be applied for different components in the ESD protection circuit, but also style of layout is of utmost importance to ensure uniform current distribution during ESD events. ESDRC first employs iLEX to extract the netlist from layout and identify the functionality of each layout object through LVS of the extracted netlist and the schematic. Specific ESD design rules are then checked for each layout object identified.","abstract_has_math":false,"creators":["Li, Qiao"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Sun-Mo (Steve) Kang"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:21:22Z","date_published":"2015-09-25T20:21:22Z","updated_at":"2026-07-22T22:26:17Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9996651"],"render_values":[{"text":"(MiAaPQ)AAI9996651","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81993","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Sun-Mo (Steve) Kang"]},{"key":"dc:creator","label":"Author","values":["Li, Qiao"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:21:22Z","10000-01-01","2001"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81993","(MiAaPQ)AAI9996651"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["ESD design rule checking is different from the conventional design rule checking in that not only different rules have to be applied for different components in the ESD protection circuit, but also style of layout is of utmost importance to ensure uniform current distribution during ESD events. ESDRC first employs iLEX to extract the netlist from layout and identify the functionality of each layout object through LVS of the extracted netlist and the schematic. Specific ESD design rules are then checked for each layout object identified.","Made available in DSpace on 2015-09-25T20:21:22Z (GMT). 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ESDRC first employs iLEX to extract the netlist from layout and identify the functionality of each layout object through LVS of the extracted netlist and the schematic. Specific ESD design rules are then checked for each layout object identified.","Made available in DSpace on 2015-09-25T20:21:22Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9996651.pdf: 5021310 bytes, checksum: 1677a8e8f5134e6c07ca1447cc9841dd (MD5) Previous issue date: 2001","Embargo set by: Seth Robbins for item 83274 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","121 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001."],"dc:identifier":["http://hdl.handle.net/2142/81993","(MiAaPQ)AAI9996651"],"dc:language":["eng"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Layout Extraction Including Substrate Parasitics for ESD Protection Circuits and Design Rule Checking"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:17Z"}