Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits

This thesis presents algorithmic techniques that can be used during the logic synthesis phase of the VLSI design flow to reduce the total power consumption in VLSI circuits. These techniques are applicable to circuit implementations based upon static CMOS technology, but are independent of factors such as the specific fabrication process employed or the particular design style practiced. We study four problems in the area of low power logic synthesis: (1) low power logic synthesis of sc XOR based circuits (2) low power multiplexer decomposition (3) low power technology decomposition of simple gates under a general delay model (4) low power retiming of sequential circuits under a general delay model. In the first problem we provide a polynomial time algorithm for the synthesis of power optimal sc XOR trees under a zero delay model. In the second problem we propose efficient heuristics for low multiplexer decomposition which take into account the spatial correlation of data signals in a multiplexer tree and consequently synthesize near power optimal decompositions. In the third and fourth problems we propose an estimate of the switching activity in a circuit that takes into account glitching. We then use the estimate to perform low power technology decomposition and low power retiming to attain power savings under a general delay model.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Narayanan, Unni Krishnan

Contributors dc:contributor

• Liu, C.L.

• Computer Science

Language dc:language

eng

Identifier

(MiAaPQ)AAI9834719

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81911