{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81911"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81911","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits","abstract":"This thesis presents algorithmic techniques that can be used during the logic synthesis phase of the VLSI design flow to reduce the total power consumption in VLSI circuits. These techniques are applicable to circuit implementations based upon static CMOS technology, but are independent of factors such as the specific fabrication process employed or the particular design style practiced. We study four problems in the area of low power logic synthesis: (1) low power logic synthesis of sc XOR based circuits (2) low power multiplexer decomposition (3) low power technology decomposition of simple gates under a general delay model (4) low power retiming of sequential circuits under a general delay model. In the first problem we provide a polynomial time algorithm for the synthesis of power optimal sc XOR trees under a zero delay model. In the second problem we propose efficient heuristics for low multiplexer decomposition which take into account the spatial correlation of data signals in a multiplexer tree and consequently synthesize near power optimal decompositions. In the third and fourth problems we propose an estimate of the switching activity in a circuit that takes into account glitching. We then use the estimate to perform low power technology decomposition and low power retiming to attain power savings under a general delay model.","abstract_html":"This thesis presents algorithmic techniques that can be used during the logic synthesis phase of the VLSI design flow to reduce the total power consumption in VLSI circuits. These techniques are applicable to circuit implementations based upon static CMOS technology, but are independent of factors such as the specific fabrication process employed or the particular design style practiced. We study four problems in the area of low power logic synthesis: (1) low power logic synthesis of sc XOR based circuits (2) low power multiplexer decomposition (3) low power technology decomposition of simple gates under a general delay model (4) low power retiming of sequential circuits under a general delay model. In the first problem we provide a polynomial time algorithm for the synthesis of power optimal sc XOR trees under a zero delay model. In the second problem we propose efficient heuristics for low multiplexer decomposition which take into account the spatial correlation of data signals in a multiplexer tree and consequently synthesize near power optimal decompositions. In the third and fourth problems we propose an estimate of the switching activity in a circuit that takes into account glitching. We then use the estimate to perform low power technology decomposition and low power retiming to attain power savings under a general delay model.","abstract_has_math":false,"creators":["Narayanan, Unni Krishnan"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Liu, C.L."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:20:58Z","date_published":"2015-09-25T20:20:58Z","updated_at":"2026-07-22T22:26:17Z","subjects":["Computer Science"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9834719"],"render_values":[{"text":"(MiAaPQ)AAI9834719","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81911","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Liu, C.L."]},{"key":"dc:creator","label":"Author","values":["Narayanan, Unni Krishnan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:20:58Z","10000-01-01","1998"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81911","(MiAaPQ)AAI9834719"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis presents algorithmic techniques that can be used during the logic synthesis phase of the VLSI design flow to reduce the total power consumption in VLSI circuits. These techniques are applicable to circuit implementations based upon static CMOS technology, but are independent of factors such as the specific fabrication process employed or the particular design style practiced. We study four problems in the area of low power logic synthesis: (1) low power logic synthesis of sc XOR based circuits (2) low power multiplexer decomposition (3) low power technology decomposition of simple gates under a general delay model (4) low power retiming of sequential circuits under a general delay model. In the first problem we provide a polynomial time algorithm for the synthesis of power optimal sc XOR trees under a zero delay model. In the second problem we propose efficient heuristics for low multiplexer decomposition which take into account the spatial correlation of data signals in a multiplexer tree and consequently synthesize near power optimal decompositions. In the third and fourth problems we propose an estimate of the switching activity in a circuit that takes into account glitching. We then use the estimate to perform low power technology decomposition and low power retiming to attain power savings under a general delay model.","Made available in DSpace on 2015-09-25T20:20:58Z (GMT). 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These techniques are applicable to circuit implementations based upon static CMOS technology, but are independent of factors such as the specific fabrication process employed or the particular design style practiced. We study four problems in the area of low power logic synthesis: (1) low power logic synthesis of sc XOR based circuits (2) low power multiplexer decomposition (3) low power technology decomposition of simple gates under a general delay model (4) low power retiming of sequential circuits under a general delay model. In the first problem we provide a polynomial time algorithm for the synthesis of power optimal sc XOR trees under a zero delay model. In the second problem we propose efficient heuristics for low multiplexer decomposition which take into account the spatial correlation of data signals in a multiplexer tree and consequently synthesize near power optimal decompositions. In the third and fourth problems we propose an estimate of the switching activity in a circuit that takes into account glitching. We then use the estimate to perform low power technology decomposition and low power retiming to attain power savings under a general delay model.","Made available in DSpace on 2015-09-25T20:20:58Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9834719.pdf: 4144648 bytes, checksum: 5eff723587eb987b26df2719ddc01d72 (MD5) Previous issue date: 1998","Embargo set by: Seth Robbins for item 83192 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","83 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998."],"dc:identifier":["http://hdl.handle.net/2142/81911","(MiAaPQ)AAI9834719"],"dc:language":["eng"],"dc:subject":["Computer Science"],"dc:title":["Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:17Z"}