Worst-Case Timing Analysis of Concurrently Executing DMA I/O and Programs

A cycle-stealing DMA I/O task is allowed to proceed only when the CPU does not need the system bus. As a result, the execution time of a cycle-stealing DMA I/O task is affected by a set of CPU tasks which execute concurrently with the I/O task. We discuss the problem of bounding the WCET of a cycle-stealing DMA I/O task under a workload which consists of a set of independent CPU tasks. Each CPU task has an arbitrary release time. We use the dynamic programming technique to bound the WCET of the I/O task.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

1997

Author dc:creator

• Huang, Tai-Yi

Contributors dc:contributor

• Liu, Jane W.S.

• Computer Science

Language dc:language

eng

Identifier

(MiAaPQ)AAI9812633

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81899