Low-Power Reconfigurable Digital Signal Processing

We present a design methodology for low-power communication systems. This is based on the concept of DAT and intellectual property (IP) core generators. Energy-optimum parameters are obtained via DAT, and are fed into IP core generators, which generate a synthesizable VHDL description of the IP core. The IP cores are synthesized via commercial logic synthesis tools. The proposed design methodology has been applied to generate receiver gate-level netlist for several channels including the microwave and cable channels.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Goel, Manish

Contributors dc:contributor

• Naresh Shanbhag

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9990006

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81349