1-Gs/s, 14-Bit Digital -to -Analog Converter and Track -and -Hold Amplifier

A 1-GS/s, 14-bit track-and-hold amplifier (THA) has been studied as the second half of this dissertation research. The THA is a key subcircuit in a data acquisition and conversion system. The input buffer of the THA employs an open-loop linearization technique to reduce distortion and increase bandwidth. The hold-mode feedthrough is reduced by the replica switch technique. The parasitic capacitance compensation technique is employed to further improve the signal bandwidth of the THA. Simulation results indicate that the parasitic capacitance compensation technique improves the bandwidth by approximately a factor of 5. The THA circuit was also designed using a 60-GHz fT InGaP/GaAs HBT technology. Simulation results are 83-dB SFDR at 100-MHz sampling frequency, 65-dB SFDR at 1-GHz sampling frequency, and 60-dB SFDR at 2-GHz sampling frequency under all Nyquist conditions.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Seo, Dongwon

Contributors dc:contributor

• Feng, Milton

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9971188

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81342