{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81342"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81342","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"1-Gs/s, 14-Bit Digital -to -Analog Converter and Track -and -Hold Amplifier","abstract":"A 1-GS/s, 14-bit track-and-hold amplifier (THA) has been studied as the second half of this dissertation research. The THA is a key subcircuit in a data acquisition and conversion system. The input buffer of the THA employs an open-loop linearization technique to reduce distortion and increase bandwidth. The hold-mode feedthrough is reduced by the replica switch technique. The parasitic capacitance compensation technique is employed to further improve the signal bandwidth of the THA. Simulation results indicate that the parasitic capacitance compensation technique improves the bandwidth by approximately a factor of 5. The THA circuit was also designed using a 60-GHz fT InGaP/GaAs HBT technology. Simulation results are 83-dB SFDR at 100-MHz sampling frequency, 65-dB SFDR at 1-GHz sampling frequency, and 60-dB SFDR at 2-GHz sampling frequency under all Nyquist conditions.","abstract_html":"A 1-GS/s, 14-bit track-and-hold amplifier (THA) has been studied as the second half of this dissertation research. The THA is a key subcircuit in a data acquisition and conversion system. The input buffer of the THA employs an open-loop linearization technique to reduce distortion and increase bandwidth. The hold-mode feedthrough is reduced by the replica switch technique. The parasitic capacitance compensation technique is employed to further improve the signal bandwidth of the THA. Simulation results indicate that the parasitic capacitance compensation technique improves the bandwidth by approximately a factor of 5. The THA circuit was also designed using a 60-GHz fT InGaP/GaAs HBT technology. Simulation results are 83-dB SFDR at 100-MHz sampling frequency, 65-dB SFDR at 1-GHz sampling frequency, and 60-dB SFDR at 2-GHz sampling frequency under all Nyquist conditions.","abstract_has_math":false,"creators":["Seo, Dongwon"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Feng, Milton"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:10:39Z","date_published":"2015-09-25T20:10:39Z","updated_at":"2026-07-22T22:26:16Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9971188"],"render_values":[{"text":"(MiAaPQ)AAI9971188","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81342","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Feng, Milton"]},{"key":"dc:creator","label":"Author","values":["Seo, Dongwon"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:10:39Z","10000-01-01","2000"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81342","(MiAaPQ)AAI9971188"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["A 1-GS/s, 14-bit track-and-hold amplifier (THA) has been studied as the second half of this dissertation research. The THA is a key subcircuit in a data acquisition and conversion system. The input buffer of the THA employs an open-loop linearization technique to reduce distortion and increase bandwidth. The hold-mode feedthrough is reduced by the replica switch technique. The parasitic capacitance compensation technique is employed to further improve the signal bandwidth of the THA. Simulation results indicate that the parasitic capacitance compensation technique improves the bandwidth by approximately a factor of 5. The THA circuit was also designed using a 60-GHz fT InGaP/GaAs HBT technology. Simulation results are 83-dB SFDR at 100-MHz sampling frequency, 65-dB SFDR at 1-GHz sampling frequency, and 60-dB SFDR at 2-GHz sampling frequency under all Nyquist conditions.","Made available in DSpace on 2015-09-25T20:10:39Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9971188.pdf: 3742667 bytes, checksum: d27c015a310706bc1226e161264f1350 (MD5) Previous issue date: 2000","Embargo set by: Seth Robbins for item 82623 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","119 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000."]},{"key":"dc:title","label":"Title","values":["1-Gs/s, 14-Bit Digital -to -Analog Converter and Track -and -Hold Amplifier"]}]}],"canonical_facts":{"dc:contributor":["Feng, Milton"],"dc:creator":["Seo, Dongwon"],"dc:date":["2015-09-25T20:10:39Z","10000-01-01","2000"],"dc:description":["A 1-GS/s, 14-bit track-and-hold amplifier (THA) has been studied as the second half of this dissertation research. The THA is a key subcircuit in a data acquisition and conversion system. The input buffer of the THA employs an open-loop linearization technique to reduce distortion and increase bandwidth. The hold-mode feedthrough is reduced by the replica switch technique. The parasitic capacitance compensation technique is employed to further improve the signal bandwidth of the THA. Simulation results indicate that the parasitic capacitance compensation technique improves the bandwidth by approximately a factor of 5. The THA circuit was also designed using a 60-GHz fT InGaP/GaAs HBT technology. Simulation results are 83-dB SFDR at 100-MHz sampling frequency, 65-dB SFDR at 1-GHz sampling frequency, and 60-dB SFDR at 2-GHz sampling frequency under all Nyquist conditions.","Made available in DSpace on 2015-09-25T20:10:39Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9971188.pdf: 3742667 bytes, checksum: d27c015a310706bc1226e161264f1350 (MD5) Previous issue date: 2000","Embargo set by: Seth Robbins for item 82623 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","119 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000."],"dc:identifier":["http://hdl.handle.net/2142/81342","(MiAaPQ)AAI9971188"],"dc:language":["eng"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["1-Gs/s, 14-Bit Digital -to -Analog Converter and Track -and -Hold Amplifier"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:16Z"}