A Fast Timing Simulator With Accurate Reduced-Order Interconnect Models

The methodologies and techniques developed in this research are implemented in a fast interconnect/timing simulator, ILLIADS-I. In their practical implementation the robustness of the interconnect models is further improved to achieve absolute numerical stability in addition to their theoretical passivity and stability. Unlike other approaches, the interconnect simulation methods in ILLIADS-I do not handle the interconnect network separately for obtaining and then placing a corresponding stamp into a SPICE-like simulator. The accuracy and speed have been demonstrated for a number of circuits for various loads and input waveforms. Experimental results show that ILLIADS-I is both accurate and fast. The speed advantage is shown to increase with the circuit size for multilevel interconnect networks with nonlinear driver and load circuits. In addition to ILLIADS-I, a stand-alone linear interconnect simulator called iPINTA (Illinois Passive Interconnect Analyzer) has been developed. This simulator is a complete tool for analyzing linear multiport interconnect networks based on interconnect simulation principles described in the thesis.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Kutuk, Haydar

Contributors dc:contributor

• Kang, Sung-Mo (Steve)

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9955639

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81322