{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81322"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81322","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"A Fast Timing Simulator With Accurate Reduced-Order Interconnect Models","abstract":"The methodologies and techniques developed in this research are implemented in a fast interconnect/timing simulator, ILLIADS-I. In their practical implementation the robustness of the interconnect models is further improved to achieve absolute numerical stability in addition to their theoretical passivity and stability. Unlike other approaches, the interconnect simulation methods in ILLIADS-I do not handle the interconnect network separately for obtaining and then placing a corresponding stamp into a SPICE-like simulator. The accuracy and speed have been demonstrated for a number of circuits for various loads and input waveforms. Experimental results show that ILLIADS-I is both accurate and fast. The speed advantage is shown to increase with the circuit size for multilevel interconnect networks with nonlinear driver and load circuits. In addition to ILLIADS-I, a stand-alone linear interconnect simulator called iPINTA (Illinois Passive Interconnect Analyzer) has been developed. This simulator is a complete tool for analyzing linear multiport interconnect networks based on interconnect simulation principles described in the thesis.","abstract_html":"The methodologies and techniques developed in this research are implemented in a fast interconnect/timing simulator, ILLIADS-I. In their practical implementation the robustness of the interconnect models is further improved to achieve absolute numerical stability in addition to their theoretical passivity and stability. Unlike other approaches, the interconnect simulation methods in ILLIADS-I do not handle the interconnect network separately for obtaining and then placing a corresponding stamp into a SPICE-like simulator. The accuracy and speed have been demonstrated for a number of circuits for various loads and input waveforms. Experimental results show that ILLIADS-I is both accurate and fast. The speed advantage is shown to increase with the circuit size for multilevel interconnect networks with nonlinear driver and load circuits. In addition to ILLIADS-I, a stand-alone linear interconnect simulator called iPINTA (Illinois Passive Interconnect Analyzer) has been developed. This simulator is a complete tool for analyzing linear multiport interconnect networks based on interconnect simulation principles described in the thesis.","abstract_has_math":false,"creators":["Kutuk, Haydar"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Kang, Sung-Mo (Steve)"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:10:34Z","date_published":"2015-09-25T20:10:34Z","updated_at":"2026-07-22T22:26:16Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9955639"],"render_values":[{"text":"(MiAaPQ)AAI9955639","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81322","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kang, Sung-Mo (Steve)"]},{"key":"dc:creator","label":"Author","values":["Kutuk, Haydar"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:10:34Z","10000-01-01","2000"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81322","(MiAaPQ)AAI9955639"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The methodologies and techniques developed in this research are implemented in a fast interconnect/timing simulator, ILLIADS-I. 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