Power and Voltage Drop Analyses in VLSI Circuits

The bottleneck of voltage drop analysis lies in the matrix inversion that is involved in solving the circuit equations of the power/ground bus. To remove the bottleneck, we proposed an algorithm to quickly estimate the cycle-by-cycle maximum voltage drop values of a circuit driven by an input sequence. Based on the rank of the estimates, a small set of input vectors is selected for detailed analysis to identify the worst-case voltage drop behavior. The pruning strategy has been applied to a set of industry designs and is found to be on average three times faster than direct network analysis. Compared to a straightforward approach of using the total power as the estimator, the proposed algorithm demonstrates higher run-time efficiency and better consistency with the actual simulation results.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Yuan, Li-Pen

Contributors dc:contributor

• Kang, Sung-Mo (Steve)

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9945039

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81301