{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81301"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81301","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Power and Voltage Drop Analyses in VLSI Circuits","abstract":"The bottleneck of voltage drop analysis lies in the matrix inversion that is involved in solving the circuit equations of the power/ground bus. To remove the bottleneck, we proposed an algorithm to quickly estimate the cycle-by-cycle maximum voltage drop values of a circuit driven by an input sequence. Based on the rank of the estimates, a small set of input vectors is selected for detailed analysis to identify the worst-case voltage drop behavior. The pruning strategy has been applied to a set of industry designs and is found to be on average three times faster than direct network analysis. Compared to a straightforward approach of using the total power as the estimator, the proposed algorithm demonstrates higher run-time efficiency and better consistency with the actual simulation results.","abstract_html":"The bottleneck of voltage drop analysis lies in the matrix inversion that is involved in solving the circuit equations of the power/ground bus. To remove the bottleneck, we proposed an algorithm to quickly estimate the cycle-by-cycle maximum voltage drop values of a circuit driven by an input sequence. Based on the rank of the estimates, a small set of input vectors is selected for detailed analysis to identify the worst-case voltage drop behavior. The pruning strategy has been applied to a set of industry designs and is found to be on average three times faster than direct network analysis. Compared to a straightforward approach of using the total power as the estimator, the proposed algorithm demonstrates higher run-time efficiency and better consistency with the actual simulation results.","abstract_has_math":false,"creators":["Yuan, Li-Pen"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Kang, Sung-Mo (Steve)"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:10:27Z","date_published":"2015-09-25T20:10:27Z","updated_at":"2026-07-22T22:26:16Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9945039"],"render_values":[{"text":"(MiAaPQ)AAI9945039","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81301","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kang, Sung-Mo (Steve)"]},{"key":"dc:creator","label":"Author","values":["Yuan, Li-Pen"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:10:27Z","10000-01-01","1999"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81301","(MiAaPQ)AAI9945039"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The bottleneck of voltage drop analysis lies in the matrix inversion that is involved in solving the circuit equations of the power/ground bus. To remove the bottleneck, we proposed an algorithm to quickly estimate the cycle-by-cycle maximum voltage drop values of a circuit driven by an input sequence. Based on the rank of the estimates, a small set of input vectors is selected for detailed analysis to identify the worst-case voltage drop behavior. The pruning strategy has been applied to a set of industry designs and is found to be on average three times faster than direct network analysis. Compared to a straightforward approach of using the total power as the estimator, the proposed algorithm demonstrates higher run-time efficiency and better consistency with the actual simulation results.","Made available in DSpace on 2015-09-25T20:10:27Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9945039.pdf: 5858628 bytes, checksum: e9d1670819ffea584bbb0f8d32e2eaec (MD5) Previous issue date: 1999","Embargo set by: Seth Robbins for item 82582 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","140 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999."]},{"key":"dc:title","label":"Title","values":["Power and Voltage Drop Analyses in VLSI Circuits"]}]}],"canonical_facts":{"dc:contributor":["Kang, Sung-Mo (Steve)"],"dc:creator":["Yuan, Li-Pen"],"dc:date":["2015-09-25T20:10:27Z","10000-01-01","1999"],"dc:description":["The bottleneck of voltage drop analysis lies in the matrix inversion that is involved in solving the circuit equations of the power/ground bus. To remove the bottleneck, we proposed an algorithm to quickly estimate the cycle-by-cycle maximum voltage drop values of a circuit driven by an input sequence. Based on the rank of the estimates, a small set of input vectors is selected for detailed analysis to identify the worst-case voltage drop behavior. The pruning strategy has been applied to a set of industry designs and is found to be on average three times faster than direct network analysis. Compared to a straightforward approach of using the total power as the estimator, the proposed algorithm demonstrates higher run-time efficiency and better consistency with the actual simulation results.","Made available in DSpace on 2015-09-25T20:10:27Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9945039.pdf: 5858628 bytes, checksum: e9d1670819ffea584bbb0f8d32e2eaec (MD5) Previous issue date: 1999","Embargo set by: Seth Robbins for item 82582 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","140 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999."],"dc:identifier":["http://hdl.handle.net/2142/81301","(MiAaPQ)AAI9945039"],"dc:language":["eng"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Power and Voltage Drop Analyses in VLSI Circuits"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:16Z"}