The Monolithic Integration of Enhancement- and Depletion-Mode High Electron Mobility Transistors for Low-Power and High-Speed Circuit Applications in the Lattice -Matched Indium Phosphide Material System

By using a buried-Pt process in conjunction with proper heterostructure design, a procedure for the fabrication of enhancement-mode HEMTs (E-HEMTs) has been developed. Following the full characterization of E-HEMT devices, a heterostructure was then designed for the monolithic integration of E-HEMTs and D-HEMTs, using a two-level etch-stop process. Devices were successfully fabricated and characterized which showed the viability of a directcoupled FET logic (DCFL) circuit technology in the InP material system. To demonstrate the feasibility of this technology, DCFL ring oscillators were fabricated and tested. These circuits successfully demonstrated high-speed, low-power performance while utilizing only a single voltage supply.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Mahajan, Aaditya

Contributors dc:contributor

• Adesida, Ilesanmi

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9944931

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81295