Modeling, Simulation and Design of EOS/ESD Protection Devices and Circuits in Silicon-on-Insulator Technology

For the first time, a circuit level simulation tool for CMOS-on-SOI ESD protection networks is presented. The simulator, SOI-iETSIM, has built-in device models for completely coupled electrothermal simulation of SOI protection devices operating in the high current regime. The implementation of thermal models in a circuit level simulator for SOI circuits is discussed. Modeling the floating body effects in SOI MOSFETs and their effect on the device operation in the snapback mode is also discussed. The implementation of the parasitic BJT in the SOI MOSFET model is different from previously published models. Device simulation examples and an SOI-ESD protection circuit simulation example are also presented.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Raha, Prasun Kumar

Contributors dc:contributor

• Rosenbaum, Elyse

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9834733

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81229