{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81229"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81229","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Modeling, Simulation and Design of EOS/ESD Protection Devices and Circuits in Silicon-on-Insulator Technology","abstract":"For the first time, a circuit level simulation tool for CMOS-on-SOI ESD protection networks is presented. The simulator, SOI-iETSIM, has built-in device models for completely coupled electrothermal simulation of SOI protection devices operating in the high current regime. The implementation of thermal models in a circuit level simulator for SOI circuits is discussed. Modeling the floating body effects in SOI MOSFETs and their effect on the device operation in the snapback mode is also discussed. The implementation of the parasitic BJT in the SOI MOSFET model is different from previously published models. Device simulation examples and an SOI-ESD protection circuit simulation example are also presented.","abstract_html":"For the first time, a circuit level simulation tool for CMOS-on-SOI ESD protection networks is presented. The simulator, SOI-iETSIM, has built-in device models for completely coupled electrothermal simulation of SOI protection devices operating in the high current regime. The implementation of thermal models in a circuit level simulator for SOI circuits is discussed. Modeling the floating body effects in SOI MOSFETs and their effect on the device operation in the snapback mode is also discussed. The implementation of the parasitic BJT in the SOI MOSFET model is different from previously published models. Device simulation examples and an SOI-ESD protection circuit simulation example are also presented.","abstract_has_math":false,"creators":["Raha, Prasun Kumar"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:10:09Z","date_published":"2015-09-25T20:10:09Z","updated_at":"2026-07-22T22:26:15Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9834733"],"render_values":[{"text":"(MiAaPQ)AAI9834733","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81229","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse"]},{"key":"dc:creator","label":"Author","values":["Raha, Prasun Kumar"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:10:09Z","10000-01-01","1998"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81229","(MiAaPQ)AAI9834733"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["For the first time, a circuit level simulation tool for CMOS-on-SOI ESD protection networks is presented. The simulator, SOI-iETSIM, has built-in device models for completely coupled electrothermal simulation of SOI protection devices operating in the high current regime. The implementation of thermal models in a circuit level simulator for SOI circuits is discussed. Modeling the floating body effects in SOI MOSFETs and their effect on the device operation in the snapback mode is also discussed. The implementation of the parasitic BJT in the SOI MOSFET model is different from previously published models. Device simulation examples and an SOI-ESD protection circuit simulation example are also presented.","Made available in DSpace on 2015-09-25T20:10:09Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9834733.pdf: 3154176 bytes, checksum: a6b03edf8a64947ed2ac667e50353ff4 (MD5) Previous issue date: 1998","Embargo set by: Seth Robbins for item 82510 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","107 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998."]},{"key":"dc:title","label":"Title","values":["Modeling, Simulation and Design of EOS/ESD Protection Devices and Circuits in Silicon-on-Insulator Technology"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse"],"dc:creator":["Raha, Prasun Kumar"],"dc:date":["2015-09-25T20:10:09Z","10000-01-01","1998"],"dc:description":["For the first time, a circuit level simulation tool for CMOS-on-SOI ESD protection networks is presented. The simulator, SOI-iETSIM, has built-in device models for completely coupled electrothermal simulation of SOI protection devices operating in the high current regime. The implementation of thermal models in a circuit level simulator for SOI circuits is discussed. Modeling the floating body effects in SOI MOSFETs and their effect on the device operation in the snapback mode is also discussed. The implementation of the parasitic BJT in the SOI MOSFET model is different from previously published models. Device simulation examples and an SOI-ESD protection circuit simulation example are also presented.","Made available in DSpace on 2015-09-25T20:10:09Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 9834733.pdf: 3154176 bytes, checksum: a6b03edf8a64947ed2ac667e50353ff4 (MD5) Previous issue date: 1998","Embargo set by: Seth Robbins for item 82510 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","107 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998."],"dc:identifier":["http://hdl.handle.net/2142/81229","(MiAaPQ)AAI9834733"],"dc:language":["eng"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Modeling, Simulation and Design of EOS/ESD Protection Devices and Circuits in Silicon-on-Insulator Technology"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:15Z"}