Architecture and CAD for Nanoscale and Three-Dimensional FPGA

To maximize the potential performance gain of 3D integrated circuit architectures, an SSTA engine was developed to deal with both uncorrelated and correlated variations in 3D FPGAs. The effects of intra-die and inter-die variation are considered. Using the 3D physical design tool TPR as a base, a new 3D routing algorithm is developed, which improves the average performance of two-layer designs by over 22% and three-layer designs by over 27%.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Dong, Chen

Contributors dc:contributor

• Chen, Deming

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3455707

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81158