Design and ESD Protection of Wideband, Radio Frequency Integrated Circuits in CMOS Technologies

Finally, the work concludes with a summary of the design of a 6.25-Gb/s serial I/O transceiver for backplane communications that implements error correction coding to reduce equalization power and transmitter output swing. The design of the transmit driver with pre-emphasis equalization, receiver amplifier, and voltage controlled oscillator is described. The I/O transceiver is fully ESD-protected with an expected 2-kV human body model failure threshold.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Bhatia, Karan Singh

Contributors dc:contributor

• Rosenbaum, Elyse

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3337699

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81088