Reliability and Security Engine: A Processor-Level Framework for Application -Aware Detection and Recovery

Our results show a decrease in overhead by 53% and a decrease in false positives by approximately 12% as compared to a duplication of all instructions. We detect all control logic errors that affect the instruction wakeup and scheduling mechanism. The combined hardware overhead due to the framework and modules is less than 10%. Our ongoing research is targeted towards implementing the framework and the modules on a Xilinx FPGA and towards refining the application analysis tools to detect key application characteristics, and then translating these characteristics into hardware modules that can be embedded into the framework.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Nakka, Nithin Manikyam

Contributors dc:contributor

• Ravishanker K. Iyer

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3242950

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80982