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University of Illinois at Urbana-Champaign
Analysis and Design of Soft-Error Tolerant Circuits
Abstract
dc:descriptionWe propose a cost-effective testing scheme for verification of proof-of-concept soft-error tolerant designs. It is based on the observation that crosstalk noise can be intentionally introduced into a dense layout to emulate SETS. It has been implemented on a test chip featuring the TPTT technique.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Electrical and Computer Engineering
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2015
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Zhang, Ming
- Contributors dc:contributor
-
- Shanbhag, Naresh R.
Subjects
dc:subject × 1Rights
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
- (MiAaPQ)AAI3223763
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/80968