Matching on -Chip Data Storage to Telecommunication and Media Application Properties

For configurable SRAM, data storage savings in the range of 29% static power and 6% dynamic power are achieved without sacrificing code performance. When slight performance degradation can be tolerated, the compiler uses profile feedback to realize an average of 51.7% static and 9.4% dynamic power reduction.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Hunter, Hillery Catriona

Contributors dc:contributor

• Hwu, Wen-Mei W.

• Computer Science

Language dc:language

eng

Identifier

(MiAaPQ)AAI3160894

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80890