Noise -Tolerant Digital System Design

In addition to ISI, jitter also limits performance in high-speed I/O links. A discrete-time model that comprehends both transmit and receive jitter is presented. Typical I/O channels are shown to amplify high-frequency transmit jitter limiting the performance of equalization and multilevel signaling schemes. Design techniques to mitigate the effect of jitter are also presented.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Balamurugan, Ganesh

Contributors dc:contributor

• Naresh Shanbhag

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3153241

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80871