{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/80871"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/80871","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Noise -Tolerant Digital System Design","abstract":"In addition to ISI, jitter also limits performance in high-speed I/O links. A discrete-time model that comprehends both transmit and receive jitter is presented. Typical I/O channels are shown to amplify high-frequency transmit jitter limiting the performance of equalization and multilevel signaling schemes. Design techniques to mitigate the effect of jitter are also presented.","abstract_html":"In addition to ISI, jitter also limits performance in high-speed I/O links. A discrete-time model that comprehends both transmit and receive jitter is presented. Typical I/O channels are shown to amplify high-frequency transmit jitter limiting the performance of equalization and multilevel signaling schemes. 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