Characterization, Design, and Modeling of on -Chip Electrostatic Discharge Protection Devices

In this dissertation, extensive results are presented on characterization, design, and modeling of on-chip ESD protection devices. Specifically, simulator-independent circuit-level compact models for ESD protection NMOSFETs and diodes are developed using the Verilog-A language. Model confirmations are obtained through experimental data of a 0.6-mum, and a 0.13-mum CMOS technology. Small-signal and large-signal models are provided to ensure accurate ac and transient simulation. Improved avalanche multiplication factor equations are used to avoid convergence problems. Key modeling parameters are analyzed and important elements identified for accurate capture of the trigger voltage. Various trigger mechanisms are then studied to further understand the NMOS transient snapback behavior. Compact models of the on-resistance are proposed to incorporate the self-heating effect. Investigations on the turn-on behaviors of ESD protection MOSFETs and diodes reveal clear voltage overshooting with the help of an improved VFTLP (Very Fast Transmission Line Pulsing) system. Next, the ESD robustness of a 0.13-mum CMOS technology is carefully evaluated with design considerations given. Last, design techniques of RC-triggered, MOSFET based power clamps are discussed. A compact, timed-shutoff power clamp is proposed for area reduction and performance improvement.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Li, Junjun

Contributors dc:contributor

• Rosenbaum, Elyse

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3130970

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80861