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University of Illinois at Urbana-Champaign
Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests
Abstract
dc:descriptionWe use circuit delay bounding based on a set of linear constraints, obtained from testing some paths in the circuit robustly, to investigate how well such tests cover distributed delay defects. Unfortunately, our experimental results using the above method show robust tests may not cover distributed delay defects very well.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Electrical Engineering
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2015
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Sharma, Manish
- Contributors dc:contributor
-
- Patel, Janak H.
Subjects
dc:subject × 1Rights
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
- (MiAaPQ)AAI3101968
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/80842