Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology

Domino logic is known to consume more dynamic power than static logic. Low-voltage swing clock domino logic family is developed for substantial dynamic power saving. Delay-constrained power optimization algorithm allocates low supply voltage to logic gates such that dynamic power is minimized with timing constraint. Timing accuracy is ensured by accounting for timing variations due to gate-to-source voltage and input arrival time difference.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Jung, Seong-Ook

Contributors dc:contributor

• Kang, Sung-Mo (Steve)

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3044130

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80764