{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/80764"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/80764","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology","abstract":"Domino logic is known to consume more dynamic power than static logic. Low-voltage swing clock domino logic family is developed for substantial dynamic power saving. Delay-constrained power optimization algorithm allocates low supply voltage to logic gates such that dynamic power is minimized with timing constraint. Timing accuracy is ensured by accounting for timing variations due to gate-to-source voltage and input arrival time difference.","abstract_html":"Domino logic is known to consume more dynamic power than static logic. Low-voltage swing clock domino logic family is developed for substantial dynamic power saving. Delay-constrained power optimization algorithm allocates low supply voltage to logic gates such that dynamic power is minimized with timing constraint. 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