Design for ESD Reliability in High-Frequency Mixed-Signal Integrated Circuits

The design of on-chip ESD protection has become increasingly critical and difficult because of shrinking device feature sizes, high operating speed, and system-on-a-chip (SoC) environment. A complex ESD protection network can be easily exposed during normal operation and can cause the degradation of internal circuit performance. The ESD noise, defined as the loss introduced by ESD stress and protection network, can be caused by three mechanisms: I/O protection induced signal loss, mixed-signal coupling through power protection circuits, and latent damage. In this work, we have presented the characterization of the ESD noise. The effect of the ESD protection network on the noise performance of sensitive circuits is investigated with a test chip processed in a 0.18-mum CMOS technology. Experimental results demonstrate a critical relationship between ESD reliability and power/ground (PG) coupling: ESD robustness and PG coupling are conflicting design goals. We have presented a novel noise-aware design technique for superior noise margin and improved ESD reliability. The use of hierarchical electrostatic discharge (HED) provides a low impedance discharge path for any ESD event. The estimation of maximum PG voltage in digital circuits is critical to determine an optimal topology of protection circuits subject to noise constraints. Experimental results demonstrate the effectiveness of this method.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Lee, Jaesik

Contributors dc:contributor

• Kang, Sung-Mo (Steve)

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3023113

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80735