University of Illinois at Urbana-Champaign
Design and Analysis of Fault-Tolerant Processor Arrays for Numerical Applications
Abstract
dc:descriptionThe availability of fast devices in low cost and high density technologies promises a major breakthrough in future supercomputer designs, especially in the design of highly concurrent processors. Locally interconnected processor arrays, such as systotic arrays, are well suited to efficiently implement a major class of numerical algorithms due to their massive parallelism and regular structure. However, the successful operation of a processor array depends very much on the correctness of all the processing elements in the array. Any single faulty processor may easily jeopardize the results of the whole system. This makes the fault tolerance a very important issue in the design of processor arrays, and is the subject of this thesis.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Computer Science
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2014
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Chen, Chien-Yi
Subjects
dc:subject × 1Identifiers
dc:identifier.*- Identifier
- (UMI)AAI8721604
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/69573