Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 64 for “"processing elements"”.
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Analog Signal Processing Elements for Energy-Constrained Platforms
Energy constrained processing poses a number of challenges that have resulted in tremendous innovations over the past decade. Shrinking supply voltages and limited clock speeds have placed an emphasis on processing efficiency over the raw throughput of a processor. One of the approaches to increase …
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The Ape Machine: A Novel Stochastic Computer Based on A Set of Autonomous Processing Elements
Made available in DSpace on 2014-12-10T19:07:12Z (GMT). No. of bitstreams: 1 7317670.pdf: 3565970 bytes, checksum: 62223b1d47f334596935173503d83878 (MD5) Previous issue date: 1973
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Micro-architectural analysis of SPACERAM processing element
… multiple banks of DRAM combined with an array of processing elements. Such an architecture facilitates very high processor-memory bandwidth and hence allows for applications requiring orders of magnitude higher processing and update rates per DRAM than any current hardware. The array of processing …
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Recovery from transient faults in wavefront processor arrays
A transient fault in an array of processing elements results in an inconsistent or incorrect state in the processing element. If the erroneous information has already propagated before detection occurs, then the neighboring processing elements can also be in an incorrect state. Restarting the …
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Array -Based Direct Writing of Micro/nano Scale Structures
Applications of these integrated processing elements have been demonstrated by using them to print micro/nano scale patterns using the electro-hydrodynamic (EHD) printing process.
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Diastolic arrays : throughput-driven reconfigurable computing
… diastolic arrays. Diastolic arrays are arrays of processing elements that communicate exclusively through First-In First-Out (FIFO) queues, and provide hardware support to guarantee bandwidth and buffer space for all data transfers. FIFO control implies that a module idles if its input FIFOs are …
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Performance analysis of partitioned multistage cube network and adaptive routed single-stage cube network
Parallel processing has emerged to meet today's high demand of computationally intensive applications. In a parallel processing machine, the interconnection network is a major factor affecting the machine’s overall performance in terms of speed and versatility. This research presents an analysis of …
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Personalized Computer Architecture as Contextual Partitioning for Speech Recognition
… is entering an era of hundreds to thousands of processing elements per chip, yet no known parallelism form scales to that degree. To address this problem, we investigate the foundation of a computer architecture where processing elements and memory are contextually partitioned based upon facets …
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Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems
… in 2018 anticipated to contain thousands of processing elements on-chip and billions of processing elements system-wide. To prevent the interconnect from dominating the overall cost of future systems, there is a critical need for scalable interconnects that capture the communication …
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Processor Arrays for Problems in Computational Physics (Parallel)
… consisting of thousands of relatively simple processing elements, becomes possible. An example of such an architecture is the Goodyear Aerospace Massively Parallel Processor, which was originally conceived as a machine to support high-speed image processing. Starting from this existing system …
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Design and Analysis of Fault-Tolerant Processor Arrays for Numerical Applications
… depends very much on the correctness of all the processing elements in the array. Any single faulty processor may easily jeopardize the results of the whole system. This makes the fault tolerance a very important issue in the design of processor arrays, and is the subject of this thesis.
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Next-generation safety-critical systems using COTS based homogeneous multi-core processors and heterogeneous MPSoCS
… hardware manufacturers are integrating multiple processing elements such as CPU clusters, GPU, programmable logic (PL), and AI accelerators into a single multiprocessor system-on-chip (MPSoC). One of the common attributes of these high-performance multicore processors and MPSoCs is having a …
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A Study of Improving the Parallel Performance of VASP.
… VASP's performance deteriorated after about 17 processing elements (PEs), due to network contention. Subsequent modifications that restrict communication amongst VASP processes, together with additional support for threading, allowed VASP to scale up to 112 PEs, the maximum number that was …
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High Performance Architecture using Speculative Threads and Dynamic Memory Management Hardware
… to multi-core systems with several hundreds of processing elements. In this dissertation, I address how the performance of modern processing systems can be improved, while attempting to reduce hardware complexity and energy consumptions. My research described here tackles both central processing …
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NON-VOLATILE IN-MEMORY COMPUTING WITH SKYRMIONS AND PHASE CHANGE MEMORIES
… associated with data movement between memory and processing elements in the conventional von Neumann architectures, is a crucial design technique for enabling ultra-low power intelligent edge devices. Due to power/area versus throughput trade-offs (such as to increase the complexity of periphery …
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Scheduling parallel real-time tasks that allow imprecise results
Imprecise computation and parallel processing are two techniques for avoiding timing faults and tolerating hardware faults in hard real-time systems. When a result of the desired quality cannot be produced in time, hard real-time systems can produce an intermediate result of acceptable quality by …
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Median and morphological filtering of images in real time using an FPGA-based custom computing platform
… the design and implementation of real-time image-processing tasks on a custom computing platform called Splash-2. The tasks that have been implemented are image histogram generation, median filtering using 3X3 neighborhoods, and morphological dilation and erosion. These problems are …
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Design of a Power-aware Dataflow Processor Architecture
… What is needed is a class of special purpose processing elements which are more energy efficient for the purpose of computation. In the past, special purpose microcontrollers have been designed which are energy efficient for the targeted application space. However, reuse of the same design …
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Exploiting Multigrain Parallelism in Pairwise Sequence Search on Emergent CMP Architectures
… an nVIDIA GeForce General Purpose Graphics Processing Unit (GPGPU). Cell Broadband Engine: We parallelize the Smith-Waterman algorithm within a Cell node by performing a blocked data decomposition of the dynamic programming matrix followed by pipelined execution of the blocks across the …
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Bus scheduling implementation on the cell processor
… a heterogeneous chip system containing one Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs), each having an internal independent local storage memory. In this thesis, using CBEA as a platform, I implemented an interrupt based scheduling framework that uses Element …
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