The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design)

Turn-around time is becoming a crucial problem in integrated circuit design. Thus, Programmable Logic Arrays (PLA's) have become popular means with which to implement circuits. Their regular (i.e., matrix) structure allows for easy initial design and quick changes at later stages of design. PLA's, however, waste space, and so some method for reducing them has been sought. The SQUEEZE algorithm is used in reducing PLA's. It does not guarantee the minimality of its results, but it is able to produce near minimal results in a reasonable amount of cpu time.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Krolikoski, Stanley Joseph

• Computer Science

Identifier

(UMI)AAI8521810

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69542