{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/69542"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/69542","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design)","abstract":"Turn-around time is becoming a crucial problem in integrated circuit design. Thus, Programmable Logic Arrays (PLA's) have become popular means with which to implement circuits. Their regular (i.e., matrix) structure allows for easy initial design and quick changes at later stages of design. PLA's, however, waste space, and so some method for reducing them has been sought. The SQUEEZE algorithm is used in reducing PLA's. It does not guarantee the minimality of its results, but it is able to produce near minimal results in a reasonable amount of cpu time.","abstract_html":"Turn-around time is becoming a crucial problem in integrated circuit design. Thus, Programmable Logic Arrays (PLA's) have become popular means with which to implement circuits. Their regular (i.e., matrix) structure allows for easy initial design and quick changes at later stages of design. PLA's, however, waste space, and so some method for reducing them has been sought. The SQUEEZE algorithm is used in reducing PLA's. It does not guarantee the minimality of its results, but it is able to produce near minimal results in a reasonable amount of cpu time.","abstract_has_math":false,"creators":["Krolikoski, Stanley Joseph"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-12-15T19:25:39Z","date_published":"2014-12-15T19:25:39Z","updated_at":"2026-07-22T22:26:01Z","subjects":["Computer Science"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI8521810"],"render_values":[{"text":"(UMI)AAI8521810","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/69542","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Krolikoski, Stanley Joseph"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-12-15T19:25:39Z","10000-01-01","1985"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/69542","(UMI)AAI8521810"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Turn-around time is becoming a crucial problem in integrated circuit design. Thus, Programmable Logic Arrays (PLA's) have become popular means with which to implement circuits. Their regular (i.e., matrix) structure allows for easy initial design and quick changes at later stages of design. PLA's, however, waste space, and so some method for reducing them has been sought. The SQUEEZE algorithm is used in reducing PLA's. It does not guarantee the minimality of its results, but it is able to produce near minimal results in a reasonable amount of cpu time.","The thesis is divided into three main sections. First, there is an introduction to PLA's. Next there is an in-depth discussion of SQUEEZE. Finally, there are statistics presented which indicate the actual performance of the programs which implement SQUEEZE.","Made available in DSpace on 2014-12-15T19:25:39Z (GMT). No. of bitstreams: 1 8521810.pdf: 5289753 bytes, checksum: d1b56149874e40bcb11080a576f27cea (MD5) Previous issue date: 1985","Embargo set by: Seth Robbins for item 69708 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","205 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985."]},{"key":"dc:title","label":"Title","values":["The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design)"]}]}],"canonical_facts":{"dc:creator":["Krolikoski, Stanley Joseph"],"dc:date":["2014-12-15T19:25:39Z","10000-01-01","1985"],"dc:description":["Turn-around time is becoming a crucial problem in integrated circuit design. Thus, Programmable Logic Arrays (PLA's) have become popular means with which to implement circuits. Their regular (i.e., matrix) structure allows for easy initial design and quick changes at later stages of design. PLA's, however, waste space, and so some method for reducing them has been sought. The SQUEEZE algorithm is used in reducing PLA's. It does not guarantee the minimality of its results, but it is able to produce near minimal results in a reasonable amount of cpu time.","The thesis is divided into three main sections. First, there is an introduction to PLA's. Next there is an in-depth discussion of SQUEEZE. Finally, there are statistics presented which indicate the actual performance of the programs which implement SQUEEZE.","Made available in DSpace on 2014-12-15T19:25:39Z (GMT). No. of bitstreams: 1 8521810.pdf: 5289753 bytes, checksum: d1b56149874e40bcb11080a576f27cea (MD5) Previous issue date: 1985","Embargo set by: Seth Robbins for item 69708 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","205 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985."],"dc:identifier":["http://hdl.handle.net/2142/69542","(UMI)AAI8521810"],"dc:subject":["Computer Science"],"dc:title":["The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design)"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:01Z"}