Back to results

University of Illinois at Urbana-Champaign

Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers

Abstract

dc:description

The work presented in this thesis deals with the development of a fast and fairly accurate Computer Aided Design software for simulating very-large-scale-integrated (VLSI) circuits. The methods rely on piecewise linearized nonlinear elements in the circuits.

Degree

thesis:*
Name thesis:degree_name
Ph.D.
Level thesis:degree_level
Dissertation
Discipline thesis:degree_discipline
Electrical Engineering
Grantor
University of Illinois at Urbana-Champaign
Year dc:date
2014

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Tejayadi, Ongky
Contributors dc:contributor
  • Hajj, Ibrahim N.

Subjects

dc:subject × 2

Identifiers

dc:identifier.*
Identifier
(UMI)AAI8815430
OAI identifier oai:identifier
oai:www.ideals.illinois.edu:2142/69391

Chain of custody

source
Harvested from
University of Illinois - Urbana-Champaign
Base URL
www.ideals.illinois.edu/oai-pmh
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Tejayadi, Ongky. Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers. Dissertation thesis, University of Illinois at Urbana-Champaign, 2014. http://hdl.handle.net/2142/69391