{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/69391"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/69391","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers","abstract":"The work presented in this thesis deals with the development of a fast and fairly accurate Computer Aided Design software for simulating very-large-scale-integrated (VLSI) circuits. The methods rely on piecewise linearized nonlinear elements in the circuits.","abstract_html":"The work presented in this thesis deals with the development of a fast and fairly accurate Computer Aided Design software for simulating very-large-scale-integrated (VLSI) circuits. The methods rely on piecewise linearized nonlinear elements in the circuits.","abstract_has_math":false,"creators":["Tejayadi, Ongky"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Hajj, Ibrahim N."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-12-15T19:05:32Z","date_published":"2014-12-15T19:05:32Z","updated_at":"2026-07-22T22:26:00Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI8815430"],"render_values":[{"text":"(UMI)AAI8815430","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/69391","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hajj, Ibrahim N."]},{"key":"dc:creator","label":"Author","values":["Tejayadi, Ongky"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-12-15T19:05:32Z","10000-01-01","1988"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/69391","(UMI)AAI8815430"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The work presented in this thesis deals with the development of a fast and fairly accurate Computer Aided Design software for simulating very-large-scale-integrated (VLSI) circuits. The methods rely on piecewise linearized nonlinear elements in the circuits.","The piecewise linear approaches explored in this work are (1) A fast piecewise linear Gauss-Seidel waveform relaxation method. (2) A slower but more accurate piecewise linear method based on simplices. (3) A Gauss-Seidel piecewise linear method with dynamic partitioning.","Also described in a mixed method which combines the fast piecewise linear method and the dynamic partitioning method. The circuit to be analyzed is partitioned into dc-connected subcircuits and then sequenced for analysis. Small subcircuits are solved using the fast piecewise linear method while large subcircuits, including the strongly-connected components in the circuit, are solved using the dynamic partitioning method.","A parallel implementation of the Gauss-Seidel piecewise linear method with dynamic partitioning on a uniprocessor computer is studied. Algorithms for the parallel implementation of the dynamic partitioning approach on a multiprocessor with shared memory (Alliant FX/8) are also explained in detail.","The piecewise linear methods presented in this work have been implemented in a set of programs called PLATINUM. The waveforms generated by PLATINUM are fairly accurate as compared to SPICE2, and the speedup for a uniprocessor machine is over two orders of magnitude, while the parallel implementation gives an additional 4 to 6 times speed improvements.","Made available in DSpace on 2014-12-15T19:05:32Z (GMT). No. of bitstreams: 1 8815430.pdf: 3747772 bytes, checksum: acdc618071bcb24e9f4430701dc0f2a5 (MD5) Previous issue date: 1988","Embargo set by: Seth Robbins for item 69557 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","139 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988."]},{"key":"dc:title","label":"Title","values":["Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers"]}]}],"canonical_facts":{"dc:contributor":["Hajj, Ibrahim N."],"dc:creator":["Tejayadi, Ongky"],"dc:date":["2014-12-15T19:05:32Z","10000-01-01","1988"],"dc:description":["The work presented in this thesis deals with the development of a fast and fairly accurate Computer Aided Design software for simulating very-large-scale-integrated (VLSI) circuits. The methods rely on piecewise linearized nonlinear elements in the circuits.","The piecewise linear approaches explored in this work are (1) A fast piecewise linear Gauss-Seidel waveform relaxation method. (2) A slower but more accurate piecewise linear method based on simplices. (3) A Gauss-Seidel piecewise linear method with dynamic partitioning.","Also described in a mixed method which combines the fast piecewise linear method and the dynamic partitioning method. The circuit to be analyzed is partitioned into dc-connected subcircuits and then sequenced for analysis. Small subcircuits are solved using the fast piecewise linear method while large subcircuits, including the strongly-connected components in the circuit, are solved using the dynamic partitioning method.","A parallel implementation of the Gauss-Seidel piecewise linear method with dynamic partitioning on a uniprocessor computer is studied. Algorithms for the parallel implementation of the dynamic partitioning approach on a multiprocessor with shared memory (Alliant FX/8) are also explained in detail.","The piecewise linear methods presented in this work have been implemented in a set of programs called PLATINUM. The waveforms generated by PLATINUM are fairly accurate as compared to SPICE2, and the speedup for a uniprocessor machine is over two orders of magnitude, while the parallel implementation gives an additional 4 to 6 times speed improvements.","Made available in DSpace on 2014-12-15T19:05:32Z (GMT). No. of bitstreams: 1 8815430.pdf: 3747772 bytes, checksum: acdc618071bcb24e9f4430701dc0f2a5 (MD5) Previous issue date: 1988","Embargo set by: Seth Robbins for item 69557 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","139 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988."],"dc:identifier":["http://hdl.handle.net/2142/69391","(UMI)AAI8815430"],"dc:subject":["Engineering, Electronics and Electrical","Computer Science"],"dc:title":["Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:00Z"}