Extraction of MOS VLSI Circuit Models Including Critical Interconnect Parasitics

As the feature sizes of Very-Large-Scale-Integrated (VLSI) circuits continue to decrease, the timing performance of a design cannot be estimated accurately without introducing the signal delay due to interconnect parasitics. Modeling interconnect parasitics directly from a circuit layout is therefore emphasized.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Su, Shun-Lin

Contributors dc:contributor

• Trick, Timothy N.

• Engineering, Electronics and Electrical
• Computer Science

Identifier

(UMI)AAI8803213

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69381