Extraction of MOS VLSI Circuit Models Including Critical Interconnect Parasitics
As the feature sizes of Very-Large-Scale-Integrated (VLSI) circuits continue to decrease, the timing performance of a design cannot be estimated accurately without introducing the signal delay due to interconnect parasitics. Modeling interconnect parasitics directly from a circuit layout is therefore emphasized.
Engineering, Electronics and Electrical, Computer Science
University of Illinois - Urbana-Champaign
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University of Illinois at Urbana-Champaign