Extraction of MOS VLSI Circuit Models Including Critical Interconnect Parasitics
type: CreativeWork
description: As the feature sizes of Very-Large-Scale-Integrated (VLSI) circuits continue to decrease, the timing performance of a design cannot be estimated accurately without introducing the signal delay due to interconnect parasitics. Modeling interconnect parasitics directly from a circuit layout is therefore emphasized.
abstract: As the feature sizes of Very-Large-Scale-Integrated (VLSI) circuits continue to decrease, the timing performance of a design cannot be estimated accurately without introducing the signal delay due to interconnect parasitics. Modeling interconnect parasitics directly from a circuit layout is therefore emphasized.
author: Su, Shun-Lin
keywords: Engineering, Electronics and Electrical, Computer Science
date published: 2014-12-15T19:05:28Z
date modified: 2026-07-22T22:26:00Z
provider: University of Illinois - Urbana-Champaign
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: University of Illinois at Urbana-Champaign

PropertyValue
property ID: Handle
value: http://hdl.handle.net/2142/69381