A compact model for silicon controlled rectifiers in low voltage CMOS processes

This thesis presents an SCR compact model for simulating ESD protection circuits. The aspects of the compact model that are necessary to reproduce measurement data, such as quasi-static I-V curves and transient voltage overshoot, are discussed. These aspects include conductivity modulation of the well resistances in the SCR, impact ionization at the N-well/P-well junction, and the influence of electric fields in the well region on carrier diffusion between the anode and cathode. Further, a detailed validation of the compact model is presented. A methodology for parameter extraction is also discussed.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Mertens, Robert

Contributors dc:contributor

• Rosenbaum, Elyse

• Complementary metal–oxide–semiconductor (CMOS)
• integrated circuits
• silicon
• silicon controlled rectifiers (SCR)
• Electrostatic discharge (ESD)

Statement dc:rights

• Copyright 2014 Robert Mertens

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/49624

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/49624