Continuous voltage-frequency scaling (CVFS)

Voltage reduction is an effective technique for minimizing energy consumption but suffers from delay penalty. Conventional methodologies require rigorous voltage regulation and workload scheduling to meet timing constraints. In this work, we observe that static CMOS is robust under low supply voltages, operates reliably during voltage transients, and exhibits similar voltage-delay characteristic across logic families. We present a continuous voltage-frequency scaling (CVFS) approach where supply variation is relaxed, and timing violations are avoided through the use of on-chip clock generation. A simple model of the critical path is presented to track circuit behavior in real time. This approach presents small overhead in data transition but enables energy optimization at the system-level. The contribution of this thesis includes the design of the digital blocks for a prototype chip in IBM 130nm technology.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2012

Author dc:creator

• Tu, Jane

Contributors dc:contributor

• Shanbhag, Naresh R.

• Minimum Energy Operation Point (MEOP)
• Dynamic Voltage Scaling (DVS)
• Compute Voltage Regulator Module (VRM)
• Continuous Voltage-Frequency Scaling (CVFS)
• Critical Path Replica (CPR)

Statement dc:rights

• Copyright 2012 Jane Tu

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/34459

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/34459