{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/34459"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/34459","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Continuous voltage-frequency scaling (CVFS)","abstract":"Voltage reduction is an effective technique for minimizing energy consumption but suffers from delay penalty. Conventional methodologies require rigorous voltage regulation and workload scheduling to meet timing constraints. In this work, we observe that static CMOS is robust under low supply voltages, operates reliably during voltage transients, and exhibits similar voltage-delay characteristic across logic families. We present a continuous voltage-frequency scaling (CVFS) approach where supply variation is relaxed, and timing violations are avoided through the use of on-chip clock generation. A simple model of the critical path is presented to track circuit behavior in real time. This approach presents small overhead in data transition but enables energy optimization at the system-level. The contribution of this thesis includes the design of the digital blocks for a prototype chip in IBM 130nm technology.","abstract_html":"Voltage reduction is an effective technique for minimizing energy consumption but suffers from delay penalty. Conventional methodologies require rigorous voltage regulation and workload scheduling to meet timing constraints. In this work, we observe that static CMOS is robust under low supply voltages, operates reliably during voltage transients, and exhibits similar voltage-delay characteristic across logic families. We present a continuous voltage-frequency scaling (CVFS) approach where supply variation is relaxed, and timing violations are avoided through the use of on-chip clock generation. A simple model of the critical path is presented to track circuit behavior in real time. This approach presents small overhead in data transition but enables energy optimization at the system-level. The contribution of this thesis includes the design of the digital blocks for a prototype chip in IBM 130nm technology.","abstract_has_math":false,"creators":["Tu, Jane"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Shanbhag, Naresh R."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2012,"date_issued":"2012-09-18T21:18:12Z","date_published":"2012-09-18T21:18:12Z","updated_at":"2026-07-22T22:25:31Z","subjects":["Minimum Energy Operation Point (MEOP)","Dynamic Voltage Scaling (DVS)","Compute Voltage Regulator Module (VRM)","Continuous Voltage-Frequency Scaling (CVFS)","Critical Path Replica (CPR)"],"languages":["en"],"rights":["Copyright 2012 Jane Tu"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/34459","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Shanbhag, Naresh R."]},{"key":"dc:creator","label":"Author","values":["Tu, Jane"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2012-09-18T21:18:12Z","2014-09-18T10:01:01Z","2012-08"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Minimum Energy Operation Point (MEOP)","Dynamic Voltage Scaling (DVS)","Compute Voltage Regulator Module (VRM)","Continuous Voltage-Frequency Scaling (CVFS)","Critical Path Replica (CPR)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2012 Jane Tu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/34459"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Voltage reduction is an effective technique for minimizing energy consumption but suffers from delay penalty. Conventional methodologies require rigorous voltage regulation and workload scheduling to meet timing constraints. In this work, we observe that static CMOS is robust under low supply voltages, operates reliably during voltage transients, and exhibits similar voltage-delay characteristic across logic families. We present a continuous voltage-frequency scaling (CVFS) approach where supply variation is relaxed, and timing violations are avoided through the use of on-chip clock generation. A simple model of the critical path is presented to track circuit behavior in real time. This approach presents small overhead in data transition but enables energy optimization at the system-level. The contribution of this thesis includes the design of the digital blocks for a prototype chip in IBM 130nm technology.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-07-20T15:36:18Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Tu_Jane.pdf: 672754 bytes, checksum: 80b9b78da3f0f11f54f999e4102a40ba (MD5)","Made available in DSpace on 2012-09-18T21:18:12Z (GMT). No. of bitstreams: 2 Tu_Jane.pdf: 672748 bytes, checksum: 3a0ecf161c6f99f3537adda921c5d1a9 (MD5) license.txt: 4056 bytes, checksum: 2ff8e7bb6364f9f3f648ffd6dab9e5ac (MD5)","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Seth Robbins (srobbins@illinois.edu) on 2012-09-18T21:21:07Z Item is restricted until 2014-09-18T21:21:01Z","Restriction data tranferred 2014-07-01T11:35:02-05:00 Original Data Group with Access UIUC Users [automated] Release Date: 2014-09-18 16:21:01 UTC Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 34733 on 2014-09-18T10:01:01Z."]},{"key":"dc:title","label":"Title","values":["Continuous voltage-frequency scaling (CVFS)"]}]}],"canonical_facts":{"dc:contributor":["Shanbhag, Naresh R."],"dc:creator":["Tu, Jane"],"dc:date":["2012-09-18T21:18:12Z","2014-09-18T10:01:01Z","2012-08"],"dc:description":["Voltage reduction is an effective technique for minimizing energy consumption but suffers from delay penalty. Conventional methodologies require rigorous voltage regulation and workload scheduling to meet timing constraints. In this work, we observe that static CMOS is robust under low supply voltages, operates reliably during voltage transients, and exhibits similar voltage-delay characteristic across logic families. We present a continuous voltage-frequency scaling (CVFS) approach where supply variation is relaxed, and timing violations are avoided through the use of on-chip clock generation. A simple model of the critical path is presented to track circuit behavior in real time. This approach presents small overhead in data transition but enables energy optimization at the system-level. The contribution of this thesis includes the design of the digital blocks for a prototype chip in IBM 130nm technology.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-07-20T15:36:18Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Tu_Jane.pdf: 672754 bytes, checksum: 80b9b78da3f0f11f54f999e4102a40ba (MD5)","Made available in DSpace on 2012-09-18T21:18:12Z (GMT). No. of bitstreams: 2 Tu_Jane.pdf: 672748 bytes, checksum: 3a0ecf161c6f99f3537adda921c5d1a9 (MD5) license.txt: 4056 bytes, checksum: 2ff8e7bb6364f9f3f648ffd6dab9e5ac (MD5)","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Seth Robbins (srobbins@illinois.edu) on 2012-09-18T21:21:07Z Item is restricted until 2014-09-18T21:21:01Z","Restriction data tranferred 2014-07-01T11:35:02-05:00 Original Data Group with Access UIUC Users [automated] Release Date: 2014-09-18 16:21:01 UTC Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 34733 on 2014-09-18T10:01:01Z."],"dc:identifier":["http://hdl.handle.net/2142/34459"],"dc:language":["en"],"dc:rights":["Copyright 2012 Jane Tu"],"dc:subject":["Minimum Energy Operation Point (MEOP)","Dynamic Voltage Scaling (DVS)","Compute Voltage Regulator Module (VRM)","Continuous Voltage-Frequency Scaling (CVFS)","Critical Path Replica (CPR)"],"dc:title":["Continuous voltage-frequency scaling (CVFS)"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:31Z"}