Clock tree synthesis under aggressive buffer insertion

In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing, and topology generation that is able to consider general buffer insertion locations. While previous work on buffered clock tree synthesis restricts potential buffer locations on merge nodes in the clock tree topology, our proposed algorithm has more freedom and thus achieves more robust slew control. Buffer insertion along routing paths had been mostly avoided previously due to the difficulty of maintaining a low skew under such aggressive buffer insertion. We developed an accurate timing analysis engine for delay and slew estimations and a balanced routing scheme for better skew reduction during clock tree synthesis. As a result, we can perform aggressive buffer insertion and maintain accurate delay information and low skew. Buffer sizing is also guided by its performance for slew control. Experiments show that our synthesis results not only honor the slew constraints but also maintain reasonable skew.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2012

Author dc:creator

• Chen, Ying-Yu

Contributors dc:contributor

• Chen, Deming

• Clock Tree
• Buffer Insertion
• Buffer Sizing
• Maze Routing
• Slew

Statement dc:rights

• Copyright 2012 Ying-Yu Chen

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/34230

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/34230