{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/34230"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/34230","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Clock tree synthesis under aggressive buffer insertion","abstract":"In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing, and topology generation that is able to consider general buffer insertion locations. While previous work on buffered clock tree synthesis restricts potential buffer locations on merge nodes in the clock tree topology, our proposed algorithm has more freedom and thus achieves more robust slew control. Buffer insertion along routing paths had been mostly avoided previously due to the difficulty of maintaining a low skew under such aggressive buffer insertion. We developed an accurate timing analysis engine for delay and slew estimations and a balanced routing scheme for better skew reduction during clock tree synthesis. As a result, we can perform aggressive buffer insertion and maintain accurate delay information and low skew. Buffer sizing is also guided by its performance for slew control. Experiments show that our synthesis results not only honor the slew constraints but also maintain reasonable skew.","abstract_html":"In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing, and topology generation that is able to consider general buffer insertion locations. While previous work on buffered clock tree synthesis restricts potential buffer locations on merge nodes in the clock tree topology, our proposed algorithm has more freedom and thus achieves more robust slew control. Buffer insertion along routing paths had been mostly avoided previously due to the difficulty of maintaining a low skew under such aggressive buffer insertion. We developed an accurate timing analysis engine for delay and slew estimations and a balanced routing scheme for better skew reduction during clock tree synthesis. As a result, we can perform aggressive buffer insertion and maintain accurate delay information and low skew. Buffer sizing is also guided by its performance for slew control. Experiments show that our synthesis results not only honor the slew constraints but also maintain reasonable skew.","abstract_has_math":false,"creators":["Chen, Ying-Yu"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chen, Deming"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2012,"date_issued":"2012-08","date_published":"2012-08","updated_at":"2026-07-22T22:25:30Z","subjects":["Clock Tree","Buffer Insertion","Buffer Sizing","Maze Routing","Slew"],"languages":["en"],"rights":["Copyright 2012 Ying-Yu Chen"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/34230","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chen, Deming"]},{"key":"dc:creator","label":"Author","values":["Chen, Ying-Yu"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2012-08","2012-09-18T21:06:58Z"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Clock Tree","Buffer Insertion","Buffer Sizing","Maze Routing","Slew"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2012 Ying-Yu Chen"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/34230"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing, and topology generation that is able to consider general buffer insertion locations. While previous work on buffered clock tree synthesis restricts potential buffer locations on merge nodes in the clock tree topology, our proposed algorithm has more freedom and thus achieves more robust slew control. Buffer insertion along routing paths had been mostly avoided previously due to the difficulty of maintaining a low skew under such aggressive buffer insertion. We developed an accurate timing analysis engine for delay and slew estimations and a balanced routing scheme for better skew reduction during clock tree synthesis. As a result, we can perform aggressive buffer insertion and maintain accurate delay information and low skew. Buffer sizing is also guided by its performance for slew control. Experiments show that our synthesis results not only honor the slew constraints but also maintain reasonable skew.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-07-18T22:19:50Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 5 ecethesis.bib: 14826 bytes, checksum: 83f626c307907f8f6363e69e3373faf6 (MD5) ack.tex: 388 bytes, checksum: 61d2e008d4ea9e6c3220cbdd339f0b0d (MD5) abs.tex: 1042 bytes, checksum: 9c809687260ffe78e5f20caec327025f (MD5) ecethesis_v1.2.tex: 48081 bytes, checksum: b18d5ace2a6ee01cfce1bbb881ebe12b (MD5) Chen_Ying-Yu.pdf: 2018909 bytes, checksum: 73b6c3678bc56e6f01876a66acf8a06c (MD5)","Made available in DSpace on 2012-09-18T21:06:58Z (GMT). No. of bitstreams: 6 Chen_Ying-Yu.pdf: 2018909 bytes, checksum: 73b6c3678bc56e6f01876a66acf8a06c (MD5) license.txt: 4058 bytes, checksum: 09094a912ca7a8c1e57dba1a4a4e5f25 (MD5) ecethesis_v1.2.tex: 48081 bytes, checksum: b18d5ace2a6ee01cfce1bbb881ebe12b (MD5) abs.tex: 1042 bytes, checksum: 9c809687260ffe78e5f20caec327025f (MD5) ack.tex: 388 bytes, checksum: 61d2e008d4ea9e6c3220cbdd339f0b0d (MD5) ecethesis.bib: 14826 bytes, checksum: 83f626c307907f8f6363e69e3373faf6 (MD5)"]},{"key":"dc:title","label":"Title","values":["Clock tree synthesis under aggressive buffer insertion"]}]}],"canonical_facts":{"dc:contributor":["Chen, Deming"],"dc:creator":["Chen, Ying-Yu"],"dc:date":["2012-08","2012-09-18T21:06:58Z"],"dc:description":["In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing, and topology generation that is able to consider general buffer insertion locations. While previous work on buffered clock tree synthesis restricts potential buffer locations on merge nodes in the clock tree topology, our proposed algorithm has more freedom and thus achieves more robust slew control. Buffer insertion along routing paths had been mostly avoided previously due to the difficulty of maintaining a low skew under such aggressive buffer insertion. We developed an accurate timing analysis engine for delay and slew estimations and a balanced routing scheme for better skew reduction during clock tree synthesis. As a result, we can perform aggressive buffer insertion and maintain accurate delay information and low skew. Buffer sizing is also guided by its performance for slew control. Experiments show that our synthesis results not only honor the slew constraints but also maintain reasonable skew.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-07-18T22:19:50Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 5 ecethesis.bib: 14826 bytes, checksum: 83f626c307907f8f6363e69e3373faf6 (MD5) ack.tex: 388 bytes, checksum: 61d2e008d4ea9e6c3220cbdd339f0b0d (MD5) abs.tex: 1042 bytes, checksum: 9c809687260ffe78e5f20caec327025f (MD5) ecethesis_v1.2.tex: 48081 bytes, checksum: b18d5ace2a6ee01cfce1bbb881ebe12b (MD5) Chen_Ying-Yu.pdf: 2018909 bytes, checksum: 73b6c3678bc56e6f01876a66acf8a06c (MD5)","Made available in DSpace on 2012-09-18T21:06:58Z (GMT). No. of bitstreams: 6 Chen_Ying-Yu.pdf: 2018909 bytes, checksum: 73b6c3678bc56e6f01876a66acf8a06c (MD5) license.txt: 4058 bytes, checksum: 09094a912ca7a8c1e57dba1a4a4e5f25 (MD5) ecethesis_v1.2.tex: 48081 bytes, checksum: b18d5ace2a6ee01cfce1bbb881ebe12b (MD5) abs.tex: 1042 bytes, checksum: 9c809687260ffe78e5f20caec327025f (MD5) ack.tex: 388 bytes, checksum: 61d2e008d4ea9e6c3220cbdd339f0b0d (MD5) ecethesis.bib: 14826 bytes, checksum: 83f626c307907f8f6363e69e3373faf6 (MD5)"],"dc:identifier":["http://hdl.handle.net/2142/34230"],"dc:language":["en"],"dc:rights":["Copyright 2012 Ying-Yu Chen"],"dc:subject":["Clock Tree","Buffer Insertion","Buffer Sizing","Maze Routing","Slew"],"dc:title":["Clock tree synthesis under aggressive buffer insertion"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:30Z"}