The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption

For signal integrity reasons, the magnitude of the parasitics generated by electrostatic discharge (ESD) protection devices has become budgeted. Such budgets restrict the protection level and implementation options of the ESD protection circuit designer. In this work, the ESD protection on high-speed serial I/O link performance is investigated. Simulations are used to determine the effect of the parasitic ESD capacitance on the equalization required to maintain a specific bit error rate (BER). Then, the simulation results are converted into power estimates to demonstrate the power versus reliability trade-off. Essentially, rather than approaching the effect of ESD protection circuits as harmful, this work approaches the effect of ESD protection circuits as an engineering optimization problem which requires co-design between the printed circuit board (PCB) designer, transmitter and receiver circuit designer, and ESD protection circuit designer.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Faust, Adam

Contributors dc:contributor

• Rosenbaum, Elyse

• Electrostatic Discharge (ESD)
• Serial I/O
• Signal Integrity
• Equalization

Statement dc:rights

• © 2011 Adam Clay Faust

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/26032

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/26032