{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/26032"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/26032","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption","abstract":"For signal integrity reasons, the magnitude of the parasitics generated by electrostatic discharge (ESD) protection devices has become budgeted. Such budgets restrict the protection level and implementation options of the ESD protection circuit designer. In this work, the ESD protection on high-speed serial I/O link performance is investigated. Simulations are used to determine the effect of the parasitic ESD capacitance on the equalization required to maintain a specific bit error rate (BER). Then, the simulation results are converted into power estimates to demonstrate the power versus reliability trade-off. Essentially, rather than approaching the effect of ESD protection circuits as harmful, this work approaches the effect of ESD protection circuits as an engineering optimization problem which requires co-design between the printed circuit board (PCB) designer, transmitter and receiver circuit designer, and ESD protection circuit designer.","abstract_html":"For signal integrity reasons, the magnitude of the parasitics generated by electrostatic discharge (ESD) protection devices has become budgeted. Such budgets restrict the protection level and implementation options of the ESD protection circuit designer. In this work, the ESD protection on high-speed serial I/O link performance is investigated. Simulations are used to determine the effect of the parasitic ESD capacitance on the equalization required to maintain a specific bit error rate (BER). Then, the simulation results are converted into power estimates to demonstrate the power versus reliability trade-off. Essentially, rather than approaching the effect of ESD protection circuits as harmful, this work approaches the effect of ESD protection circuits as an engineering optimization problem which requires co-design between the printed circuit board (PCB) designer, transmitter and receiver circuit designer, and ESD protection circuit designer.","abstract_has_math":false,"creators":["Faust, Adam"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-08-25T22:09:57Z","date_published":"2011-08-25T22:09:57Z","updated_at":"2026-07-22T22:25:26Z","subjects":["Electrostatic Discharge (ESD)","Serial I/O","Signal Integrity","Equalization"],"languages":["en"],"rights":["© 2011 Adam Clay Faust"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/26032","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse"]},{"key":"dc:creator","label":"Author","values":["Faust, Adam"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-08-25T22:09:57Z","2011-08"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrostatic Discharge (ESD)","Serial I/O","Signal Integrity","Equalization"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["© 2011 Adam Clay Faust"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/26032"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["For signal integrity reasons, the magnitude of the parasitics generated by electrostatic discharge (ESD) protection devices has become budgeted. Such budgets restrict the protection level and implementation options of the ESD protection circuit designer. In this work, the ESD protection on high-speed serial I/O link performance is investigated. Simulations are used to determine the effect of the parasitic ESD capacitance on the equalization required to maintain a specific bit error rate (BER). Then, the simulation results are converted into power estimates to demonstrate the power versus reliability trade-off. Essentially, rather than approaching the effect of ESD protection circuits as harmful, this work approaches the effect of ESD protection circuits as an engineering optimization problem which requires co-design between the printed circuit board (PCB) designer, transmitter and receiver circuit designer, and ESD protection circuit designer.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2011-07-18T16:07:24Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 0_Adam_Faust_MS_THESIS_FINAL.docx: 4212447 bytes, checksum: 3cfd37f340697ba6af62700ada166099 (MD5) Faust_Adam.pdf: 1123550 bytes, checksum: 66f2ca6d4871737a83eb4596054211b6 (MD5)","Made available in DSpace on 2011-08-25T22:09:57Z (GMT). No. of bitstreams: 3 Faust_Adam.pdf: 1123550 bytes, checksum: 66f2ca6d4871737a83eb4596054211b6 (MD5) license.txt: 4059 bytes, checksum: b65ff33213d1d630903381be07afd740 (MD5) 0_Adam_Faust_MS_THESIS_FINAL.docx: 4212447 bytes, checksum: 3cfd37f340697ba6af62700ada166099 (MD5)"]},{"key":"dc:title","label":"Title","values":["The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse"],"dc:creator":["Faust, Adam"],"dc:date":["2011-08-25T22:09:57Z","2011-08"],"dc:description":["For signal integrity reasons, the magnitude of the parasitics generated by electrostatic discharge (ESD) protection devices has become budgeted. Such budgets restrict the protection level and implementation options of the ESD protection circuit designer. In this work, the ESD protection on high-speed serial I/O link performance is investigated. Simulations are used to determine the effect of the parasitic ESD capacitance on the equalization required to maintain a specific bit error rate (BER). Then, the simulation results are converted into power estimates to demonstrate the power versus reliability trade-off. Essentially, rather than approaching the effect of ESD protection circuits as harmful, this work approaches the effect of ESD protection circuits as an engineering optimization problem which requires co-design between the printed circuit board (PCB) designer, transmitter and receiver circuit designer, and ESD protection circuit designer.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2011-07-18T16:07:24Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 0_Adam_Faust_MS_THESIS_FINAL.docx: 4212447 bytes, checksum: 3cfd37f340697ba6af62700ada166099 (MD5) Faust_Adam.pdf: 1123550 bytes, checksum: 66f2ca6d4871737a83eb4596054211b6 (MD5)","Made available in DSpace on 2011-08-25T22:09:57Z (GMT). No. of bitstreams: 3 Faust_Adam.pdf: 1123550 bytes, checksum: 66f2ca6d4871737a83eb4596054211b6 (MD5) license.txt: 4059 bytes, checksum: b65ff33213d1d630903381be07afd740 (MD5) 0_Adam_Faust_MS_THESIS_FINAL.docx: 4212447 bytes, checksum: 3cfd37f340697ba6af62700ada166099 (MD5)"],"dc:identifier":["http://hdl.handle.net/2142/26032"],"dc:language":["en"],"dc:rights":["© 2011 Adam Clay Faust"],"dc:subject":["Electrostatic Discharge (ESD)","Serial I/O","Signal Integrity","Equalization"],"dc:title":["The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:26Z"}