Cache design exploration in a general purpose massively parallel architecture

Memory model design is a major part of any modern processor architecture. There are many design choices and tradeoffs to be considered, and these often need to be tightly coupled to the processing unit's arcitecure. The increased popularity of massively parallel architectures has motivated researchers to further examine the memory model tradeoffs these types of architectures and their target applications present. This thesis will focus on Rigel, a 1024-core, general purpose massively parallel architecure. I will study the memory model design tradeoffs of the Rigel cluster, a subblock of the Rigel architecure, and attempt to propose a design configuration that is suitable to the unique requirements of the Rigel architecture. Rigel is an agressive design target and requires us to focus on the area and power impact of the memory model design choices. As a result, to study the design tradeoffs, I use an approach that utlizes an RTL implementation, combined with a custom design exploration flow built on top of production quality CAD tools. This flow allows us to extract accurate power and area results for each design point and pick points that provide us with the highest perfomance density.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Venshtain, Simion

Contributors dc:contributor

• Patel, Sanjay J.

• Cache
• Interconnect
• Cache design
• Cache hierarchy
• Nonblocking cache
• RTL design exploration
• register transfer level (RTL)
• Rigel
• Massively parallel
• Accelerator

Statement dc:rights

• Copyright 2011 Simion Venshtain

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/24258

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/24258