A numerical optimization-based methodology for application robustification: transforming applications for error tolerance

There have been several attempts at correcting process variation induced errors by identifying and masking these errors at the circuit and architecture level. These approaches take up valuable die area and power on the chip. As an alternative, we explore the feasibility of an approach that allows these errors to occur freely and handles them in software at the algorithmic level. In this thesis, we present a general approach to converting applications into an error tolerant form by recasting these applications as numerical optimization problems, which can then be solved reliably via stochastic optimization. We evaluate the potential robustness and energy benefits of the proposed approach using an FPGA-based framework that emulates timing errors in the floating point unit (FPU) of a Leon3 processor. We show that stochastic versions of applications have the potential to produce good quality outputs in the face of timing errors under certain assumptions. We also show that good quality results are possible for both intrinsically robust algorithms as well as fragile applications under these assumptions.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Sloan, Joseph A.

Contributors dc:contributor

• Kumar, Rakesh

• stochastic processors
• fault tolerance
• application robustification

Statement dc:rights

• (Copyright 2011 Joseph Augustyn Sloan)

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/24206

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/24206