Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 26 for “"timing errors"”.
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Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures
… renders nanometer circuits extremely prone to timing errors that threaten system functionality and reliability. To protect circuits from timing errors, designers adopt pessimistic timing margins, which lead to energy inefficiency. This dissertation focuses on addressing the challenges related …
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A descriptive, correlational study of medication administration timing error prevalence in acute care, underreporting among acute care nurses, and the correlation to patient safety culture
Background. Medication administration timing errors are associated with patient harm. Complicated by underreporting, accurate rates have been elusive. Correlation with patient safety culture is unknown. Purpose. Guided by high reliability organization theory, this study aimed to describe individual …
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A numerical optimization-based methodology for application robustification: transforming applications for error tolerance
… attempts at correcting process variation induced errors by identifying and masking these errors at the circuit and architecture level. These approaches take up valuable die area and power on the chip. As an alternative, we explore the feasibility of an approach that allows these errors to occur …
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Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths
… of high-level synthesis to detect control errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-b reducer sharing. We introduce logic and dataflow optimizations to further reduce cost. We evaluated our technique with 12 high-level …
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Fault-Tolerant Scheduling and Broadcast Problems
… faults considered in these problems result from timing errors and communication line failures, respectively. For both problems fault-tolerant techniques are incorporated into the system and various costs are analyzed.
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Optimization of tunable silicon compatible microring filters
… has to be held at certain value to allow minimum timing errors in the sampling of the signal. Thermal tuning is used to compensate for any fabrication errors or environmental temperature fluctuations that might lead to shift in the resonant frequency. With the optimized heater design and the …
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Allocating decoupling capacitors to reduce simultaneous switching noise on chips
… in VLSI design. This kind of noise can lead to timing errors and significant circuit slowdowns, if not kept within reasonable bounds. The most common way of reducing this form of noise is the addition of decoupling capacitance on chip. However, adding decoupling capacitance can take significant …
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A comparison of timing methods in orthogonal frequency division multiplexing (OFDM) systems
… efficiently and effectively to reduce the errors. OFDM must be time synchronized to prevent inter-symbol interference (ISI) and inter-carrier interference (ICI). Many techniques exist to realize timing synchronization in OFDM systems. In this thesis, the need for timing synchronization, the …
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The effect of visual transformation on implicitly and explicitly timed bimanual drawing tasks
… whether visual transformation impacts the timing and spatial variability of explicitly and implicitly timed bimanual drawing tasks differently. To examine these issues, ten healthy participants bimanually drew various template shapes (circles, lines, vertical triangles and horizontal …
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Self-tuning dynamic voltage scaling techniques for processor design
… variations, processor designers have used more timing margins. Therefore, in a modern-day DVS processor, reducing voltage requires comparatively more performance degradation when compared to its predecessors. For this reason, this technique has a lot of room for improvement for the following …
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Design of robust ultra-low power platform for in-silicon machine learning
… models that can accurately model the hardware errors on the stochastic fabrics. The models are validated in a commercial 45 nm CMOS process and employed to evaluate the performance of machine learning kernels in the presence of hardware errors. Performance prediction of a support vector machine …
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Analysis Of Time Synchronization Errors In High Data Rate Ultrawideban
… The purpose of this Thesis is to estimate the timing accuracies required with such systems in order to achieve Bit Error Rates (BER) of the order of magnitude of 10-12 and thereby avoid overloading the correction of irreducible errors due to misaligned timing errors to a small absolute number …
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A non-intrusive fault tolerant framework for mission critical real-time systems
… As testing can only show the presence of errors, not their absence, higher levels of system dependability may be provided by the implementation of mechanisms that can protect the system from faults. We present a framework for the development of fault tolerant mission critical real-time …
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Thwarting Electromagnetic Fault Injection Attack Utilizing Timing Attack Countermeasure
… parameters such as EM-injection location and timing. We conclude that EMFI induces local timing errors implying current timing attack detection and prevention techniques can be adapted to overcome EMFI. To further validate our hypothesis, we integrate a configurable timing sensor into our …
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A new compound modulation technique for multi-channel analog video transmission on fiber
… Finally, carrier-to-noise penalty caused by timing errors and jitter effects are analyzed.
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Bio-inspired error-tolerant and energy-efficient signal processing
… (voltage overscaling), which leads to hardware timing errors. In the presence of these hardware errors, signal statistics are generated from overlapping band-pass filters with frequency redundancy. Robust techniques, such as median estimation and algorithmic noise-tolerance, are applied to …
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Completion and validation of the design of a reconfigurable image processing board
… design and to anticipate any kind of logic or timing errors in the design. This thesis describes the modifications to the original design to make it reconfigurable with proper initialization and the Hardware Simulation of the IPB, using General Simulation Program (GSP), including some comments …
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Deficits in eye movement control in children with 22q11.2 deletion syndrome.
… with 22q11.2 DS exhibited increased direction errors in the antisaccade task, increased timing errors in the DMS task, as well as decreased predictive and increased regular saccades in the predictive task. The group of children with 22q11.2 DS also exhibited an increase in saccade amplitude in …
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Energy-efficient systems for information transfer and processing
… and voltage (PVT) variations which can lead to timing errors. To leverage the great potential of NTV for energy efficiency, this dissertation develops a new statistical error compensation (SEC) technique referred to as rank decomposed SEC (RD-SEC). RD-SEC makes use of inherent redundancy in CNNs …
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Improving Per-Thread Performance on CMPs through Timing Speculation
… demands, this dissertation proposes a Timing Speculation (TS) system for CMPs that boosts core clock frequencies past their normal limits when an application demands per-thread performance and operates efficiently at nominal frequency when it demands throughput. This work's …
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